3

Integrated

Circuit

Systems, Inc.

ICS952011

0721A—07/29/03

Pin Description

PIN

PIN

PIN

#

NAME

TYPE

1

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

2

**FS0/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

3

**FS1/REF1

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

4

**FS2/REF2

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

5

GNDREF

PWR

Ground pin for the REF outputs.

6

X1

IN

Crystal input, Nominally 14.318MHz.

7

X2

OUT

Crystal output, Nominally 14.318MHz

8

GNDZ

PWR

Ground pin for the ZCLK outputs

9

ZCLK0

OUT

3.3V Hyperzip clock output.

10

ZCLK1

OUT

3.3V Hyperzip clock output.

11

VDDZ

PWR

Power supply for ZCLK clocks, nominal 3.3V

12

*(PCI_STOP#)PCICLK6

I/O

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This

input is activated by the MODE selection pin / PCI clock output.

13

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

14

**FS3/PCICLK_F0

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

15

**FS4/PCICLK_F1

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

16

*MODE0/PCICLK0

I/O

Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / PCI clock output.

17

PCICLK1

OUT

PCI clock output.

18

GNDPCI

PWR

Ground pin for the PCI outputs

19

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

20

PCICLK2

OUT

PCI clock output.

21

PCICLK3

OUT

PCI clock output.

22

PCICLK4

OUT

PCI clock output.

23

PCICLK5

OUT

PCI clock output.

24

GNDPCI

PWR

Ground pin for the PCI outputs

25

GND48

PWR

Ground pin for the 48MHz outputs

26

24_48MHz/SEL24_48#*~

I/O

24MHz/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =

24MHz.

27

12_48MHz/SEL12_48#**

I/O

12MHz/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =

12MHz.

28

VDD48

PWR

Power pin for the 48MHz output.3.3V

29

VDDAGP

PWR

Power supply for AGP clocks, nominal 3.3V

30

AGPCLK1

OUT

AGP clock output

31

AGPCLK0

OUT

AGP clock output

32

GNDAGP

PWR

Ground pin for the AGP outputs

33

Vtt_PwrGd/PD#(CPUSTOP

#)*

I/O

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs

are valid and are ready to be sampled. This is an active high input. Active low Power

Down input or active low CPU_STOP depend on B24b3 IIC selection. Default is PD#.

34

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

35

SCLK

IN

Clock pin of I2C circuitry 5V tolerant

36

VDDA

PWR

3.3V power for the PLL core.

37

GND

PWR

Ground pin.

38

IREF

OUT

This pin establishes the reference current for the differential current-mode output pairs.

This pin requires a fixed precision resistor tied to ground in order to establish the

appropriate current. 475 ohms is the standard value.

39

CPUCLKC0

OUT

"Complimentary" clocks of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

40

CPUCLKT0

OUT

"True" clocks of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

41

GNDCPU

PWR

Ground pin for the CPU outputs

42

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

43

CPUCLKC1

OUT

"Complimentary" clocks of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

44

CPUCLKT1

OUT

"True" clocks of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

45

CPU_STOP#(PD#)*

IN

Active low CPU_STOP or Active low Power Down input depend on B24b3 IIC selection.

Default is CPU_STOP#.

46

GND

PWR

Ground pin.

47

SDRAM_OUT

OUT

SDRAM seed clock output for external buffer

48

VDDSDR

PWR

Supply for SDRAM clocks, nominal 3.3V.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor

DESCRIPTION