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ICS952011 数据表(PDF) 10 Page - Renesas Technology Corp

部件名 ICS952011
功能描述  Programmable Timing Control Hub™ for P4™ processor
PDF  26 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

ICS952011 数据表(HTML) 10 Page - Renesas Technology Corp

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10
Integrated
Circuit
Systems, Inc.
ICS952011
0721A—07/29/03
I
2C Table: Function Control Register
Control
Function
Bit 7
PDEN
PD# Enable
RW
Disable
Enable
1
Bit 6
AZCLKFS
Async Zclk Freq Select in
N-programming (Mode
01, see table 3)
RW
66.6MHz
133.3MHz
1
Bit 5
WDS_EN
WD Soft Enable
RW
Disable
Enable
1
Bit 4
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 3
AZCLKFS
Async Zclk Freq Select
(Mode 10 & 11, see table
3)
RW
66MHz
132MHz
1
Bit 2
Reserved
Reserved
RW
-
1
Bit 1
AEN1
RW
0
Bit 0
AEN0
RW
0
-
-
Zclk/Agp/Pci Freq
Source Select Control
See Table 3 : ZCLK, AGP &
PCI Frequency Source
Decode Table
-
-
-
-
1PWD
-
-
Name
Pin #
Byte 0
Type
0
Table 3: ZCLK Frequency Source Decode Table
Byte0 Bit1
Byte0 Bit0
ZCLK & AGP & PCI
0
0
See Table 1, QuadRom Frequency Table
0
1
N-Programming for ZCLK/AGP/PCI
1
0
See Table 1 for AGP/PCI, B0b3 for ZCLK freq
1
1
N-Prog for AGP/PCI, B0b3 for ZCLK freq
I
2C Table: Async N-Programming Frequency Select Register
Control
Function
Bit 7
N PLL3 Div7
RW
-
-
0
Bit 6
N PLL3 Div6
RW
-
-
1
Bit 5
N PLL3 Div5
RW
-
-
0
Bit 4
N PLL3 Div4
RW
-
-
0
Bit 3
N PLL3 Div3
RW
-
-
0
Bit 2
N PLL3 Div2
RW
-
-
1
Bit 1
N PLL3 Div1
RW
-
-
1
Bit 0
N PLL3 Div0
RW
-
-
1
I
2C Table: Reserved Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
1
Bit 6
Reserved
Reserved
RW
-
-
1
Bit 5
Reserved
Reserved
RW
-
-
1
Bit 4
Reserved
Reserved
RW
-
-
1
Bit 3
Reserved
Reserved
RW
-
-
1
Bit 2
Reserved
Reserved
RW
-
-
1
Bit 1
Reserved
Reserved
RW
-
-
1
Bit 0
Reserved
Reserved
RW
-
-
1
-
Name
-
Byte 1
-
Type
1
PWD
0
PWD
0
-
-
Name
Type
The decimal
representation of N PLL2
Div (7:0) + 8 is equal to
VCO divider value for
PLL2. Default at power
up = 66.67MHz
1
-
Pin #
-
-
-
Byte 2
-
Pin #
-
-
-
-
-



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