2

Integrated

Circuit

Systems, Inc.

ICS952011

0721A—07/29/03

The ICS952011 is a two chip clock solution for desktop designs using SIS 645/645DX/648/650 style chipsets. When used with

a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary

clocks signals for such a system.

The ICS952011 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the

first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the

use of a serially programmable I

2C interface, this device can adjust the output clocks by configuring the frequency setting, the

output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each

individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting

under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

General Description

Block Diagram

Power Groups

CPUCLKT (1:0)

AGPCLK (1:0)

SDRAM_OUT

PCICLK (6:0)

PCICLKF (1:0)

I REF

ZCLK (1:0)

CPUCLKC (1:0)

PLL2

Frequency

Dividers

Programmable

Spread

PLL1

Programmable

Frequency

Dividers

STOP

Logic

12_48MHz

24_48MHz

X1

X2

XTAL

VTTPWR_GND/PD#

FS (4:0)

CPU_STOP#

PCI_STOP#

MODE 0

SEL12_48#

SEL24_48#

Control

Logic

REF (2:0)

VDD

GND

1

5

REF Output, Crystal

11

8

Hyper ZCLK outputs

28

25

12/24/48MHz, Fix Analog, Fix Digital

29

32

AGP outputs

36

37

CPU PLL, CPU Analog, MCLK

42

41

CPU_T/C outputs

48

46

SDRAM_Out

Pin Number

Description