3

Integrated

Circuit

Systems, Inc.

ICS954321

1078B—09/20/05

Pin Description (Continued)

PIN #

PIN NAME

TYPE

DESCRIPTION

33

*OEB#

IN

Active low input for enabling outputs.

1 = tri-state outputs, 0 = enable outputs

34

*OEA#

IN

Active low input for enabling outputs.

1 = tri-state outputs, 0 = enable outputs

35

SRCCLKC7

OUT

Complement clock of differential SRC clock pair.

36

SRCCLKT7

OUT

True clock of differential SRC clock pair.

37

SRCCLKC8

OUT

Complement clock of differential SRC clock pair.

38

SRCCLKT8

OUT

True clock of differential SRC clock pair.

39

GND

PWR

Ground pin.

40

SRCCLKC9

OUT

True clock of differential push-pull SRC clock pair.

41

SRCCLKT9

OUT

True clock of differential SRC clock pair.

42

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

43

CPUCLKC2_ITP/SRCCLKC10 OUT

Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output.

These are current mode outputs. External resistors are required for voltage bias.

Selected by ITP_EN input.

44

CPUCLKT2_ITP/SRCCLKT10 OUT

True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are

current mode outputs. External resistors are required for voltage bias. Selected

by ITP_EN input.

45

VDDA

PWR

3.3V power for the PLL core.

46

GNDA

PWR

Ground pin for the PLL core.

47

IREF

OUT

This pin establishes the reference current for the differential current-mode output

pairs. This pin requires a fixed precision resistor tied to ground in order to

establish the appropriate current. 475 ohms is the standard value.

48

CPUCLKC1

OUT

Complementary clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

49

CPUCLKT1

OUT

True clock of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

50

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

51

CPUCLKC0

OUT

Complementary clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

52

CPUCLKT0

OUT

True clock of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

53

GND

PWR

Ground pin.

54

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

55

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

56

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

57

X2

OUT

Crystal output, Nominally 14.318MHz

58

X1

IN

Crystal input, Nominally 14.318MHz.

59

GND

PWR

Ground pin.

60

REF

OUT

14.318 MHz reference clock.

61

FSLC/TEST_SEL

IN

3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs,

see input electrical characteristics for Vil_FS and Vih_FS values.

TEST_Sel: 3-level latched input to enable test mode.

Refer to Test Clarification Table

62

CPU_STOP#

IN

Stops all CPUCLK, except those set to be free running clocks

63

PCI_STOP#

IN

Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not

effected by this input.

64

PCICLK0

OUT

PCI clock output.