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ICS954321 数据表(PDF) 8 Page - Renesas Technology Corp

部件名 ICS954321
功能描述  Programmable Timing Control Hub™ for P4™ processor
PDF  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

ICS954321 数据表(HTML) 8 Page - Renesas Technology Corp

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8
Integrated
Circuit
Systems, Inc.
ICS954321
1078B—09/20/05
SMBus Table:Output Control Register
Control
Function
Bit 7
-
Bit 6
CPUCLK2_ITP_STOP Drive
Mode
RW
0
Bit 5
CPUCLK1_STOP Drive
Mode
RW
0
Bit 4
CPUCLK0_STOP Drive
Mode
RW
0
Bit 3
SRCCLK (10:7, 5:0), LCD
PD Drive Mode
RW
0
Bit 2
CPUCLK2_ITP PD Drive
Mode
RW
0
Bit 1
CPUCLK[1:0] PD Drive
Mode
RW
0
Bit 0
ITP_EN
SRCCLK/CPU_ITP select
Rlatch
SMBus Table: Output Control Register
Control
Function
Bit 7
SS4
LCDCLK Spread Prog Bit
4
RW
0
Bit 6
SS3
LCDCLK Spread Prog Bit
3
RW
1
Bit 5
SS2
LCDCLK Spread Prog Bit
2
RW
0
Bit 4
SS1
LCDCLK Spread Prog Bit
1
RW
0
Bit 3
SS0
LCDCLK Spread Prog Bit
0
RW
0
Bit 2
FSLC
Freq Select Bit 2
R
Latched
Bit 1
FSLB
Freq Select Bit 1
R
Latched
Bit 0
FSLA
Freq Select Bit 0
R
Latched
SMBus Table: Vendor & Revision ID Register
Control
Function
Bit 7
RID3
R
x
Bit 6
RID2
R
x
Bit 5
RID1
R
x
Bit 4
RID0
R
x
Bit 3
VID3
R
0
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
SMBus Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
0
Bit 6
BC6
RW
0
Bit 5
BC5
RW
0
Bit 4
BC4
RW
1
Bit 3
BC3
RW
0
Bit 2
BC2
RW
0
Bit 1
BC1
RW
0
Bit 0
BC0
RW
1
96Mhz
100Mhz
See Table 2: LCDCLK Freq Sel
See Table 1: PLL1 Frequency Selection
Table
0
-
-
-
-
Pin #
-
-
-
-
-
-
-
Byte 6
Pin #
Name
Type
-
-
-
Byte 8
PWD
Type
0
1
PWD
Hi-Z
Hi-Z
Driven
Driven in Pow erdow n
(PD)
Hi-Z
Driven
Driven
Driven
Reserved
0
Driven
Driven
Hi-Z
1
SRCCLK6
CPU_ITP
-
Name
Driven in CPU_STOP#
-
Hi-Z
Hi-Z
-
-
-
-
Byte 5
Pin #
-
PWD
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 17 bytes.
Byte 7
Pin #
Name
Type
-
-
-
-
-
PWD
-
REVISION ID
--
-
--
0
-
--
-
--
-
VENDOR ID
--
-
--
-
-
-
1
-
Name
Type
Byte Count Programming
b(7:0)



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