9

Integrated

Circuit

Systems, Inc.

ICS954321

1078B—09/20/05

SMBus Table: Watchdog Timer Register

Control

Function

Bit 7

WDH_EN

Watchdog Hard Alarm

Enable

RW

0

Bit 6

WDS_EN

Watchdog Soft Alarm

Enable

RW

0

Bit 5

WD Hard Status

WD Hard Alarm Status

R

X

Bit 4

WD Soft Status

WD Soft Alarm Status

R

X

Bit 3

WDTCtrl

Watch Dog Time base

Control

RW

0

Bit 2

WD2

WD Timer Bit 2

RW

1

Bit 1

WD1

WD Timer Bit 1

RW

1

Bit 0

WD0

WD Timer Bit 0

RW

1

SMBus Table: VCO Control Select Bit & WD Timer Control Register

Control

Function

Bit 7

M/N_EN

PLLM/N Programming

Enable

RW

0

Bit 6

LCDCLK/SRCCLK0 SEL

SELSRC/LCDCLK#

R

latch

Bit 5

Reserved

Reserved

RW

1

Bit 4

-

Bit 3

WD Safe Freq Source

WD Safe Freq Source

RW

0

Bit 2

WD SFC

RW

0

Bit 1

WD SFB

RW

0

Bit 0

WD SFA

RW

0

SMBus Table: VCO Frequency Control Register

Control

Function

Bit 7

N Div8

N Divider Prog bit 8

RW

X

Bit 6

N Div 9

N Divider Prog bit 9

RW

X

Bit 5

M Div5

RW

X

Bit 4

M Div4

RW

X

Bit 3

M Div3

RW

X

Bit 2

M Div2

RW

X

Bit 1

M Div1

RW

X

Bit 0

M Div0

RW

X

SMBus Table: VCO Frequency Control Register

Control

Function

Bit 7

N Div7

RW

X

Bit 6

N Div6

RW

X

Bit 5

N Div5

RW

X

Bit 4

N Div4

RW

X

Bit 3

N Div3

RW

X

Bit 2

N Div2

RW

X

Bit 1

N Div1

RW

X

Bit 0

N Div0

RW

X

SMBus Table: Spread Spectrum Control Register

Control

Function

Bit 7

SSP7

RW

X

Bit 6

SSP6

RW

X

Bit 5

SSP5

RW

X

Bit 4

SSP4

RW

X

Bit 3

SSP3

RW

X

Bit 2

SSP2

RW

X

Bit 1

SSP1

RW

X

Bit 0

SSP0

RW

X

Alarm

Enable

Alarm

Disable

1160ms Base

Disable

These Spread Spectrum bits in Byte 13

and 14 will program the spread

pecentage. It is recommended to use

ICS Spread % table for spread

programming.

The decimal representation of M and N

Divier in Byte 11 and 12 will configure the

VCO frequency. Default at power up =

latch-in or Byte 0 Rom table. VCO

Frequency = 14.318 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]

Latch

B10b(2:0)

Pin #

Byte 11

Pin #

Byte 13

-

-

-

-

-

-

Byte 9

Pin #

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Byte 10

Pin #

-

-

PWD

1

01

PWD

Disable

Enable

LCDCLK

SRCCLK0

PWD

The decimal representation of M and N

Divier in Byte 11 and 12 will configure the

VCO frequency. Default at power up =

latch-in or Byte 0 Rom table. VCO

Frequency = 14.318 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]

1

0

0

PWD

1

-

-

-

Name

Pin #

-

-

-

-

-

Name

Type

0

PWD

Byte 12

Name

Watch Dog Safe Freq

Programming bits

Type

Type

Spread Spectrum

Programming b(7:0)

Enable

Normal

M Divider Programming

bits

N Divider Programming

b(8:0)

1

Type

-

-

-

Normal

These bits represent X*290ms (or 1.16S)

the watchdog timer waits before it goes to

alarm mode. Default is 7 X 290ms = 2s.

290ms Base

Name

Reserved

Writing to these bit will configure the safe

frequency as Byte6 bit (2:0).

-

-

-

-

-

-

-

Name

Type

0