DSPIC30F datasheet(113/220 Pages) MICROCHIP

113 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 111

dsPIC30F5011/5013

17.6.2

PRESCALER SETTING

There is a programmable prescaler with integral values

ranging from 1 to 64, in addition to a fixed divide-by-2

for clock generation. The time quantum (TQ) is a fixed

unit of time derived from the oscillator period, and is

given by Equation 17-1, where FCAN is FCY (if the

CANCKS bit is set) or 4FCY (if CANCKS is clear).

EQUATION 17-1:

TIME QUANTUM FOR

CLOCK GENERATION

17.6.3

PROPAGATION SEGMENT

This part of the bit time is used to compensate physical

delay times within the network. These delay times con-

sist of the signal propagation time on the bus line and

the internal delay time of the nodes. The Prop Seg can

be programmed from 1 TQ to 8 TQ by setting the

PRSEG<2:0> bits (CiCFG2<2:0>).

17.6.4

PHASE SEGMENTS

The phase segments are used to optimally locate the

sampling of the received bit within the transmitted bit

time. The sampling point is between Phase1 Seg and

Phase2 Seg. These segments are lengthened or short-

ened by resynchronization. The end of the Phase1 Seg

determines the sampling point within a bit period. The

segment is programmable from 1 TQ to 8 TQ. Phase2

Seg provides delay to the next transmitted data transi-

tion. The segment is programmable from 1 TQ to 8 TQ,

or it may be defined to be equal to the greater of

Phase1 Seg or the information processing time (2 TQ).

The

Phase1

Seg

initialized

setting

bits

SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is

initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).

The following requirement must be fulfilled while setting

the lengths of the phase segments:

Prop Seg + Phase1 Seg > = Phase2 Seg

17.6.5

SAMPLE POINT

The sample point is the point of time at which the bus

level is read and interpreted as the value of that respec-

tive bit. The location is at the end of Phase1 Seg. If the

bit timing is slow and contains many TQ, it is possible to

specify multiple sampling of the bus line at the sample

point. The level determined by the CAN bus then corre-

sponds to the result from the majority decision of three

values. The majority samples are taken at the sample

point and twice before with a distance of TQ/2. The

CAN module allows the user to choose between sam-

pling three times at the same point or once at the same

point, by setting or clearing the SAM bit (CiCFG2<6>).

Typically, the sampling of the bit should take place at

about 60 - 70% through the bit time, depending on the

system parameters.

17.6.6

SYNCHRONIZATION

To compensate for phase shifts between the oscillator

frequencies of the different bus stations, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the location of the edge to the expected time (Synchro-

nous Segment). The circuit will then adjust the values

of Phase1 Seg and Phase2 Seg. There are 2

mechanisms used to synchronize.

17.6.6.1

Hard Synchronization

Hard synchronization is only done whenever there is a

‘recessive’ to ‘dominant’ edge during bus Idle indicating

the start of a message. After hard synchronization, the

bit time counters are restarted with the Sync Seg. Hard

synchronization forces the edge which has caused the

hard synchronization to lie within the synchronization

segment of the restarted bit time. If a hard synchroniza-

tion is done, there will not be a resynchronization within

that bit time.

17.6.6.2

Resynchronization

As a result of resynchronization, Phase1 Seg may be

lengthened or Phase2 Seg may be shortened. The

amount of lengthening or shortening of the phase

buffer segment has an upper bound known as the syn-

chronization jump width, and is specified by the

SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-

chronization jump width will be added to Phase1 Seg or

subtracted from Phase2 Seg. The resynchronization

jump width is programmable between 1 TQ and 4 TQ.

The following requirement must be fulfilled while setting

the SJW<1:0> bits:

Phase2 Seg > Synchronization Jump Width

Note:

FCAN must not exceed 30 MHz. If

CANCKS = 0, then FCY must not exceed

7.5 MHz.

TQ = 2 (BRP<5:0> + 1) / FCAN

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