DSPIC30F datasheet(13/220 Pages) MICROCHIP

13 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 11

dsPIC30F5011/5013

2.0

CPU ARCHITECTURE

OVERVIEW

2.1

Core Overview

This section contains a brief overview of the CPU

architecture of the dsPIC30F. For additional hard-

ware and programming information, please refer to

the

dsPIC30F

Family

Reference

Manual

and

the

dsPIC30F

Programmer’s

Reference

Manual

respectively.

The core has a 24-bit instruction word. The Program

Counter (PC) is 23-bits wide with the Least Significant

(LS) bit always clear (refer to Section 3.1), and the

Most Significant (MS) bit is ignored during normal pro-

gram execution, except for certain specialized instruc-

tions. Thus, the PC can address up to 4M instruction

words of user program space. An instruction pre-fetch

mechanism is used to help maintain throughput. Pro-

gram loop constructs, free from loop count manage-

ment overhead, are supported using the DO and

REPEAT

instructions, both of which are interruptible at

any point.

The working register array consists of 16 x 16-bit regis-

ters, each of which can act as data, address or offset

registers. One working register (W15) operates as a

software stack pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory, AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2). The X and Y data space boundary is

device specific and cannot be altered by the user. Each

data word consists of 2 bytes, and most instructions

can address data either as words or bytes.

There are two methods of accessing data stored in

program memory:

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of pro-

gram space at any 16K program word boundary,

defined by the 8-bit Program Space Visibility Page

(PSVPAG) register. This lets any instruction

access program space as if it were data space,

with a limitation that the access requires an addi-

tional cycle. Moreover, only the lower 16 bits of

each instruction word can be accessed using this

method.

• Linear indirect access of 32K word pages within

program space is also possible using any working

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are

supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports bit-reversed addressing on

destination effective addresses to greatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 for details on modulo and

bit-reversed addressing.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct, Register Direct, Register

Indirect, Register Offset and Literal Offset Addressing

modes. Instructions are associated with predefined

Addressing modes, depending upon their functional

requirements.

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capability and throughput.

It features a high speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit bidirectional barrel shifter. Data in the accumula-

tor or any working register can be shifted up to 15 bits

right, or 16 bits left in a single cycle. The DSP instruc-

tions operate seamlessly with all other instructions and

have been designed for optimal real-time performance.

The MAC class of instructions can concurrently fetch

two data operands from memory while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear for all others. This has been

achieved in a transparent and flexible manner, by ded-

icating certain working registers to each address space

for the MAC class of instructions.

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction pre-fetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are reserved) and 54 interrupts. Each interrupt

is prioritized based on a user assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest), in conjunction with a predetermined ‘natural

order’. Traps have fixed priorities ranging from 8 to 15.

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