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AD9992

Rev. C | Page 43 of 92

MODE Registers

The MODE registers are used to select the field timing of the

AD9992. Typically, all of the field, V-sequence, and V-pattern

information is programmed into the AD9992 at startup. During

operation, the MODE registers allow the user to select any com-

bination of field timing to meet the requirements of the system.

The advantage of using the MODE registers in conjunction with

preprogrammed timing is that it greatly reduces the system pro-

gramming requirements during camera operation. Only a few

changed, rather than having to program all of the vertical timing

information with each camera mode change.

A basic still camera application can require six fields of vertical

timing—one for draft mode operation, one for autofocusing,

and four for still image readout. All of the register timing

information for the six fields is loaded at startup. Then, during

camera operation, the MODE registers select which field timing is

active, depending on how the camera is being used.

Table 20 shows how the MODE registers are used. The MODE

used. Any value from 1 to 7 can be selected using these three

bits. The other two registers (0x2B and 0x2C) are used to select

which of the programmed fields are used and in which order.

Up to seven fields can be used in a single MODE write. The

AD9992 starts with the field timing specified by FIELD0 and,

on the next VD, switches to the timing specified by FIELD1 and

so on. After completing the total number of fields specified by

MODE, the AD9992 repeats by starting at the first field. This

continues until a new write to the MODE register occurs. Figure 54

shows example MODE register settings for different field con-

figurations.

Note that only a write to Address 0x2C properly resets the field

counter. Therefore, when changing the values in any of the mode

registers, it is recommended that all three registers be updated

together in the same field (VD period).

Caution

The MODE registers are SCK updated by default. If they are

configured as VD-updated registers by writing Address 0xB4 =

0x03FF and Address 0xB5 = 0xFC00, the new MODE information

is updated on the second VD falling edge after the write occurs,

rather than on the first VD falling edge (see Figure 53).

Table 20. MODE Registers—VD Updated

Address

Name

Length

Description

MODE

Total number of fields to cycle through. Set from 1 to 7.

FIELD0

Selected FIELD (from FIELD registers in configurable memory) for the first field to cycle through.

FIELD1

Selected FIELD (from FIELD registers in configurable memory) for the second field to cycle through.

FIELD2

Selected FIELD (from FIELD registers in configurable memory) for the third field to cycle through.

FIELD3

Selected FIELD (from FIELD registers in configurable memory) for the fourth field to cycle through.

FIELD4

Selected FIELD (from FIELD registers in configurable memory) for the fifth field to cycle through.

FIELD5

Selected FIELD (from FIELD registers in configurable memory) for the sixth field to cycle through.

FIELD6

Selected FIELD (from FIELD registers in configurable memory) for the seventh field to cycle through.

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