AD9992BBCZ datasheet(6/92 Pages) AD

6 / 92 page

AD9992

Rev. C | Page 6 of 92

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK (See Figure 15)

CLI Clock Period

tCONV

CLI High/Low Pulse Width

12.5

Delay from CLI Rising Edge to Internal Pixel Position 0

tCLIDLY

SLAVE MODE SPECIFICATIONS (See Figure 76)

VD Falling Edge to HD Falling Edge in Slave Mode

tVDHD

VD period − 5 ×

tCONV

HD Edge to CLI Rising Edge (Only Valid if OSC_RSTB = LO)

tHDCLI

tCONV − 2

HD Edge to CLO Rising Edge (Only Valid if OSC_RSTB = HI)

tHDCLO

tCONV − 2

Inhibit Region for SHP Edge Location

tSHPINH

Edge location

AFE CLPOB PULSE WIDTH (See Figure 22 and Figure 32)1, 2

Pixels

AFE SAMPLE LOCATION (See Figure 16 and Figure 19)1

SHP Sample Edge to SHD Sample Edge

tS1

12.5

DATA OUTPUTS (See Figure 20 and Figure 21)

Output Delay from DCLK Rising Edge

tOD

Inhibited Area for DOUTPHASE Edge Location

tDOUTINH

SHDLOC + 1

SHDLOC + 15

Edge location

Pipeline Delay from SHP/SHD Sampling to DOUT

Cycles

SERIAL INTERFACE (See Figure 83)

Maximum SCK Frequency (Must Not Exceed CLI Frequency)

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

INHIBIT REGION FOR SHP AND SHD WITH RESPECT TO H-CLOCK

EDGE PLACEMENT (see Figure 19) for H*POL = 1

RETIME = 0, MASK = 0

tSHDINH

H*NEGLOC – 15

H*NEGLOC – 0

Edge location

RETIME = 0, MASK = 1

tSHDINH

H*POSLOC – 15

H*POSLOC – 0

Edge location

RETIME = 1, MASK = 0

tSHPINH

H*NEGLOC – 15

H*NEGLOC – 0

Edge location

RETIME = 1, MASK = 1

tSHPINH

H*POSLOC – 15

H*POSLOC – 0

Edge location

1 Parameter is programmable.

2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

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