ADCMP604/ADCMP605

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HYSTERESIS RESISTOR (kΩ)

CROSSOVER BIAS POINTS

Rail-to-rail inputs of this type, in both op amps and

comparators, have a dual front-end design. Certain devices are

some predetermined point in the common-mode range, a

the bias current reverses and there are changes in measured offset

voltages and currents.

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PC Board

design practice, as discussed in the Optimizing Performance

section, these comparators should be stable at any input slew

rate with no hysteresis. Broadband noise from the input stage is

observed in place of the violent chattering seen with most other

high speed comparators. With additional capacitive loading or

poor bypassing, oscillation is observed. This oscillation is due to

the high gain bandwidth of the comparator in combination with

feedback parasitics in the package and PC board. In many

applications, chattering is not harmful.