ADP1823

Rev. A | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

FB1

2

SYNC

3

FREQ

4

GND

5

UV2

6

FB2

7

COMP2

8

TRK2

24 POK1

23 BST1

22 DH1

21 SW1

20 CSL1

19 PGND1

18 DL1

17 PV

TOP VIEW

(Not to Scale)

ADP1823

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

FB1

Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and tie

the tap to FB1 to set the output voltage.

2

SYNC

Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz

and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.

3

FREQ

Frequency Select Input. Low for 300 kHz or high for 600 kHz.

4

GND

Ground. Connect to a ground plane directly beneath the ADP1823. Tie the bottom of the feedback dividers to

this GND.

5

UV2

Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2

directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.

6

FB2

Voltage Feedback Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and

tie the tap to FB2 to set the output voltage.

7

COMP2

Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2.

8

TRK2

Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider from the master

voltage. If the tracking function is not used, connect TRK2 to VREG.

9

SS2

Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period.

10

POK2

Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up

resistor from POK2 to VREG.

11

BST2

Boost Capacitor Input for Channel 2. Powers the high-side gate driver DH2. Connect a 0.22 μF to 0.47 μF

ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.

12

DH2

High-Side (Switch) Gate Driver Output for Channel 2.

13

SW2

Switch Node Connection for Channel 2.

14

CSL2

Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set the

current-limit offset.

15

PGND2

Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1823.

16

DL2

Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.

17

PV

Positive Input Voltage for Gate Drivers DL1 and DL2. Connect PV to VREG and bypass to ground with a 1

μF

capacitor.

18

DL1

Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.

19

PGND1

Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1823.

20

CSL1

Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set the

current-limit offset.

21

SW1

Switch Node Connection for Channel 1.

22

DH1

High-Side (Switch) Gate Driver Output for Channel 1.

23

BST1

Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF

ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.

24

POK1

Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up

resistor from POK1 to VREG.

25

EN1

Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off.

Enabling starts the internal LDO. Tie to IN for automatic startup.