ADP1823ACPZ-R7 datasheet(23/32 Pages) AD

23 / 32 page

ADP1823

Rev. A | Page 23 of 32

To ensure that the output voltage accuracy is not compromised

by the TRK pin being too close in voltage to the 0.6 V reference,

make sure that the final value of the master voltage is greater

than the slave regulation voltage by at least 10%, or 60 mV as

seen at the FB node, and the higher, the better. A difference of

60 mV between TRK and the 0.6 V reference produces about

3 mV of offset in the error amplifier, or 0.5%, at room

temperature, while 100 mV between them produces only

0.6 mV or 0.1% offset.

RATIOMETRIC TRACKING

Ratiometric tracking limits the output voltage to a fraction of

the master voltage. For example, the termination voltage for

DDR memories, VTT, is set to half the VDD voltage.

TIME

SLAVE VOLTAGE

MASTER VOLTAGE

Figure 31. Ratiometric Tracking

For ratiometric tracking, the simplest configuration is to tie the

TRK pin of the slave channel to the FB pin of the master channel.

This has the advantage of having the fewest components, but

the accuracy suffers as the TRK pin voltage becomes equal to

the internal reference voltage and an offset is imposed on the

error amplifier of about −18 mV at room temperature.

A more accurate solution is to provide a divider from the

master voltage that sets the TRK pin voltage to be something

lower than 0.6 V at regulation, for example, 0.5 V. The slave

channel can be viewed as having a 0.5 V external reference

supplied by the master voltage.

Once this is complete, then the FB divider for the slave voltage

is designed as in the Compensating the Voltage Mode Buck

Regulator section, except to substitute the 0.5 V reference for

the VFB voltage. The ratio of the slave output voltage to the

master voltage is a function of the two dividers:

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

TRKB

TRKT

BOT

TOP

MASTER

OUT

(63)

Another option is to add another tap to the divider for the

master voltage. Split the RBOT resistor of the master voltage into

two pieces, with the new tap at 0.5 V when the master voltage is

in regulation. This saves one resistor, but be aware that Type III

compensation on the master voltage causes the feedforward

signal of the master voltage to appear at the TRK input of the

slave channel.

By selecting the resistor values in the divider carefully, Equation 63

shows that the slave voltage output can be made to have a faster

ramp rate than that of the master voltage by setting the TRK

voltage at the slave larger than 0.6 V and RTRKB greater than

RTRKT. Make sure that the master SS period is long enough (that

is, sufficiently large SS capacitor) such that the input inrush

current does not run into the current limit of the power supply

during startup.

Setting the Channel 2 Undervoltage Threshold for

Ratiometric Tracking

If FB2 is regulated to a voltage lower than 0.6 V by configuring

TRK2 for ratiometric tracking, the Channel 2 undervoltage

threshold can be set appropriately by splitting the top resistor in

the voltage divider, as shown in Figure 32. RBOT is the same as

calculated for the compensation in Equation 63, and

TOP

(64)

550mV

750mV

POK2

UV2

FB2

CHANNEL 2

OUTPUT

VOLTAGE

RBOT

TO ERROR

AMPLIFIER

Figure 32. Setting the Channel 2 Undervoltage Threshold

The current in all the resistors is the same:

OUT

BOT

−

(65)

where:

VUV2 is 600 mV.

VFB2 is the feedback voltage value set during the ratiometric

tracking calculations.

VOUT2 is the Channel 2 output voltage.

Solving for RA and RB:

(

)

OUTA

BOT

−

(66)

(

)

BOT

−

(67)

ADP1823ACPZ-R7 数据表(PDF) 23 Page - Analog Devices

ADP1823ACPZ-R7 数据表(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载