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ADP1823

Rev. A | Page 19 of 32

Figure 25 shows a typical Bode plot of the LC filter by itself.

0dB

GAIN

FREQUENCY

LC FILTER BODE PLOT

PHASE

fLC

fESR

fCO

fSW

AFILTER

–40dB/dec

ΦFILTER

0°

–90°

–180°

–20dB/dec

Figure 25. LC Filter Bode Plot

The gain of the LC filter at crossover can be linearly

approximated from Figure 25 as

ESR

FILTER

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟

⎠

⎞

⎜

⎝

⎛

−

ESR

FILTER

log

(20)

If fESR ≈ fCO, then add another 3 dB to account for the local

difference between the exact solution and the linear

approximation above.

To compensate the control loop, the gain of the system must be

brought back up so that it is 0 dB at the desired crossover

frequency. Some gain is provided by the PWM modulation

itself, so next calculate

⎟

⎠

⎞

⎜

⎝

⎛

RAMP

MOD

log

(21)

For systems using the internal oscillator, this becomes

⎟

⎠

⎞

⎜

⎝

⎛

MOD

log

(22)

Note that if the converter is being synchronized, the ramp

voltage, VRAMP, is lower than 1.3 V by the percentage of

frequency increase over the nominal setting of the FREQ pin:

⎟

⎠

⎞

⎜

⎝

⎛

SYNC

FREQ

RAMP

(23)

The factor of 2 in the numerator takes into account that the

SYNC frequency is divided by 2 to generate the switching

frequency. For example, if the FREQ pin is set high for the

600 kHz range and a 2 MHz SYNC signal is applied, the ramp

voltage is 0.78 V. This increases the gain of the modulator by

4.4 dB in this example.

The rest of the system gain needed to reach 0 dB at crossover is

provided by the error amplifier and is covered in the compensation

design information that follows. The total gain of the system,

therefore, is given by

AT = AMOD + AFILTER + ACOMP

(24)

where:

AMOD is the gain of the PWM modulator

AFILTER is the gain of the LC filter including the effects of

the ESR zero

ACOMP is the gain of the compensated error amplifier.

Additionally, the phase of the system must be brought back up

to guarantee stability. Note from the bode plot of the filter that

the LC contributes −180° of phase shift. Additionally, because

the error amplifier is an integrator at low frequency, it

contributes an initial −90°. Therefore, before adding

compensation or accounting for the ESR zero, the system is

already down −270°. To avoid loop inversion at crossover, or

−180° phase shift, a good initial practical design is to require a

phase margin of 60°, which is therefore an overall phase loss of

−120° from the initial low frequency dc phase. The goal of the

compensation is to boost the phase back up from −270° to

−120° at crossover.

Two common compensation schemes are used, which are

sometimes referred to as Type II or Type III compensation,

depending on whether the compensation design includes two

or three poles. (Dominant pole compensations, or single pole

compensation, is referred to as Type I compensation, but

unfortunately, it is not very useful for dealing successfully with

switching regulators.)

If the zero produced by the ESR of the output capacitor provides

sufficient phase boost at crossover, Type II compensation is

adequate. If the phase boost produced by the ESR of the output

capacitor is not sufficient, another zero is added to the

compensation network, and thus Type III is used. A general rule

to determine the scheme is whether the phase contribution of

the ESR zero is greater than 70° at crossover.

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