ADP2105/ADP2106/ADP2107

Rev. 0 | Page 27 of 32

EVALUATION BOARD

EVALUATION BOARD SCHEMATIC (ADP2107-1.8)

J1

U1

EN

VCC

INPUT VOLTAGE = 2.7V TO 5.5V

OUTPUT VOLTAGE = 1.8V, 2A

VIN

GND

OUT

VCC

OUT

2

1

GND

VCC

ADP2107-1.8

EN

SS

LX2

AGND

COMP

PGND

GND

GND

GND

NC

PADDLE

LX1

PWIN2

1

2

3

4

12

11

10

9

16

15

14

13

5

6

7

8

17

R2

100kΩ

C6

68pF

C5

1nF

R1

140kΩ

C2

2µH

C3

C4

R4

0Ω

R5

NS

R3

10Ω

C7

0.1µF

C1

NC = NO CONNECT

10μF: GRM21BR61A106KE19L

22μF: GRM21BR60J226ME39L

OUT_SENSE

PWIN1

IN

GND

Figure 51. Evaluation Board Schematic of the ADP2107-1.8 (Bold Traces Are High Current Paths)

RECOMMENDED PCB BOARD LAYOUT (EVALUATION BOARD LAYOUT)

GROUND

GROUND

CONNECT THE GROUND RETURN OF

ALL POWER COMPONENTS SUCH AS

INPUT AND OUTPUT CAPACITORS TO

THE POWER GROUND PLANE.

POWER GROUND

PLANE

OUTPUT CAPACITOR

OUTPUT CAPACITOR

INPUT CAPACITOR

INPUT CAPACITOR

OUTPUT

JUMPER TO ENABLE

ENABLE

100kΩ PULL-DOWN

INPUT

PLACE THE FEEDBACK RESISTORS AS

CLOSE TO THE FB PIN AS POSSIBLE.

ADP2105/ADP2106/ADP2107

PLACE THE COMPENSATION

COMPONENTS AS CLOSE TO

THE COMP PIN AS POSSIBLE.

ANALOG GROUND PLANE

CONNECT THE GROUND RETURN OF ALL

SENSITIVE ANALOG CIRCUITRY SUCH AS

COMPENSATION AND OUTPUT VOLTAGE

DIVIDER TO THE ANALOG GROUND PLANE.

LX

LX

PGND

INDUCTOR (L)

POWER GROUND

Figure 52. Recommended Layout of Top Layer of ADP2105/ADP2106/ADP2107