Nexperia

74LVC2G38

Dual 2-input NAND gate; open drain

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

SOT1203

sot1203_po

10-04-02

10-04-06

Unit

mm

max

nom

min

0.35 0.04

1.40

1.35

1.30

1.05

1.00

0.95

0.55 0.35

0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1.0 x 0.35 mm

SOT1203

A1

b

0.20

0.15

0.12

D

E

e

e1

L

0.35

0.30

0.27

L1

0

0.5

1 mm

scale

terminal 1

index area

E

D

(4×)(2)

(8×)(2)

A

A1

e

L

L1

b

e1

e1

e1

1

8

2

7

3

6

4

5

Fig. 16. Package outline SOT1203 (XSON8)

74LVC2G38

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Product data sheet

Rev. 14 — 21 June 2022

16 / 20