AD5663

Rev. 0 | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTION

1

10

2

9

3

GND

8

DIN

4

LDAC

7

SCLK

5

CLR

6

SYNC

AD5663

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

3

GND

Ground Reference Point for All Circuitry on the Part.

4

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored.

When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part

exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write

sequence, the write is aborted.

6

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,

it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling

edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an

interrupt, and the write sequence is ignored by the device.

7

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates up to 50 MHz.

8

DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.

9

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10

Reference Voltage Input.