AD5663

Rev. 0 | Page 15 of 24

Table 8. Address Command

A2

A1

A0

ADDRESS (n)

0

0

0

DAC A

0

0

1

DAC B

0

1

0

Reserved

0

1

1

Reserved

1

1

1

All DACs

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

24th falling edge. However, if SYNC is brought high before the

24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 30).

POWER-ON RESET

The AD5663 family contains a power-on reset circuit that

controls the output voltage during power-up. The AD5663 DAC

outputs power up to 0 V, the AD5663-1 powers up to midscale,

and the output remains there until a valid write sequence is

made to the DAC. This is useful in applications where it is

important to know the state of the output of the DAC while it is

in the process of powering up. Any events on LDAC or CLR

during power-on reset are ignored.

SOFTWARE RESET

The AD5663 contains a software reset function. Command 101

is reserved for the software reset function (see Table 7). The

software reset command contains two reset modes that are

software-programmable by setting Bit DB0 in the control

register.

Table 9 shows how the state of the bit corresponds to the mode

of operation of the device. Table 10 shows the contents of the

input shift register during the software reset mode of operation.

Table 9. Software Reset Modes for the AD5663

DB0

Registers Reset to 0

0

DAC register

Input register

1 (Power-On Reset)

DAC register

Input register

LDAC register

Power-down register

Table 10. 24-Bit Input Shift Register Contents for Software Reset Command

MSB

LSB

DB23 to DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB1

DB0

x

1

0

1

x

x

x

x

1/0

Don’t care

Command bits (C2 to C0)

Address bits (A2 to A0)

Don’t care

Determines software reset mode

X

X

C2

C1

C0

A2

A1

A0

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DB23 (MSB)

DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 29. Input Register Contents

DIN

DB23

DB23

DB0

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

SYNC

SCLK

INVALID WRITE SEQUENCE:

Figure 30. SYNC Interrupt Facility