AD9510-VCOSLASHPCB datasheet(47/60 Pages) AD

47 / 60 page

AD9510

Rev. A | Page 47 of 60

Addr

(Hex)

Parameter

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Def.

Value

(Hex)

Notes

Delay Fine

Adjust 6

Not Used

5-Bit Fine Delay <5:1>

Not

Used

Min. Delay

Value

Not Used

OUTPUTS

LVPECL OUT0

Not Used

Output Level

<3:2>

Power-Down <1:0>

OFF

LVPECL OUT1

Not Used

Output Level

<3:2>

Power-Down <1:0>

LVPECL OUT2

Not Used

Output Level

<3:2>

Power-Down <1:0>

LVPECL OUT3

Not Used

Output Level

<3:2>

Power-Down <1:0>

LVDS_CMOS

OUT 4

Not Used

CMOS

Inverted

Driver On

Logic

Select

Output Level

<2:1>

Output

Power

LVDS, ON

LVDS_CMOS

OUT 5

Not Used

CMOS

Inverted

Driver On

Logic

Select

Output Level

<2:1>

Output

Power

LVDS, ON

LVDS_CMOS

OUT 6

Not Used

CMOS

Inverted

Driver On

Logic

Select

Output Level

<2:1>

Output

Power

LVDS, OFF

LVDS_CMOS

OUT 7

Not Used

CMOS

Inverted

Driver On

Logic

Select

Output Level

<2:1>

Output

Power

LVDS, OFF

Not Used

CLK1 AND

CLK2

Input

Receivers

Clocks Select,

Power-Down

(PD) Options

Not Used

CLKs in

REFIN PD

CLK

PLL

CLK2

CLK1

Select

CLK IN

All Clocks

ON, Select

CLK1

46, 47

Not Used

DIVIDERS

Divider 0

Low Cycles <7:4>

High Cycles <3:0>

Divide by 2

Divider 0

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 1

Low Cycles <7:4>

High Cycles <3:0>

Divide by 2

Divider 1

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 2

Low Cycles <7:4>

High Cycles <3:0>

Divide by 4

Divider 2

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 3

Low Cycles <7:4>

High Cycles <3:0>

Divide by 8

Divider 3

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 4

Low Cycles <7:4>

High Cycles <3:0>

Divide by 2

Divider 4

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 5

Low Cycles <7:4>

High Cycles <3:0>

Divide by 4

Divider 5

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 6

Low Cycles <7:4>

High Cycles <3:0>

Divide by 2

AD9510-VCO/PCB 数据表(PDF) 47 Page - Analog Devices

AD9510-VCO/PCB 数据表(HTML) 47 Page - Analog Devices

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AD9510-VCO/PCB 数据表(PDF) 47 Page - Analog Devices

AD9510-VCO/PCB 数据表(HTML) 47 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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链接网址

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