AD9510-VCOSLASHPCB datasheet(55/60 Pages) AD

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AD9510

Rev. A | Page 55 of 60

Reg.

Addr.

(Hex) Bit(s) Name

Description

<5>

Force

Forces Individual Outputs to the State Specified in Start (Above)

This Function Requires That Nosync (Below) Also Be Set (Default = 0b)

OUT0

(4B)

(OUT1)

(4D)

(OUT2)

(4F)

(OUT3)

(51)

(OUT4)

(53)

(OUT5)

(55)

(OUT6)

(57)

(OUT7)

<6>

Nosync

Ignore Chip-Level Sync Signal (Default = 0b)

OUT0

(4B)

(OUT1)

(4D)

(OUT2)

(4F)

(OUT3)

(51)

(OUT4)

(53)

(OUT5)

(55)

(OUT6)

(57)

(OUT7)

<7>

Bypass Divider

Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b)

OUT0

(4B)

(OUT1)

(4D)

(OUT2)

(4F)

(OUT3)

(51)

(OUT4)

(53)

(OUT5)

(55)

(OUT6)

(57)

(OUT7)

<0>

SYNC Detect Enable 1 = Enable SYNC Detect (Default = 0b)

<1>

SYNC Select

1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles

0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles

<2>

Soft SYNC

Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s polarity is

reversed. That is, a high level forces selected outputs into a known state, and a high > low transition

triggers a sync (default = 0b).

<3>

Dist Ref Power-

Down

1 = Power-Down the References for the Distribution Section (Default = 0b)

<4>

SYNC Power-Down 1 = Power-Down the SYNC (Default = 0b)

<6:5> FUNCTION Pin

Select

<6>

<5>

Function

RESETB (Default)

SYNCB

Test Only; Do Not Use

PDB

<7>

Not Used

<7:0>

Not Used

<0>

Update Registers

A 1 written to this bit updates all registers and transfers all serial control port register buffer contents to

the control registers on the next rising SCLK edge. This is a self-clearing bit; a 0 does not have to be

written to clear it.

<7:1>

Not Used

END

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