GTRA412852FC

12

Rev. 03.1, 2022-1-27

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The information in this document is subject to change without notice.

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H-37248-4_pd_10-10-2012

S

D1

D2

G1

G2

Pin

Description

D1

Drain Device 1 (main)

D2

Drain Device 2 (peak)

G1

Gate Device 1 (main)

G2

Gate Device 2 (peak)

S

Source (flange)

Pinout Diagram (top view)

Main

Peak

Bias Sequencing

Bias ON

1. Ensure RF is turned off

2. Apply pinch-off voltage of –5 V to the gate

3. Apply nominal drain voltage

4. Bias gate to desired quiescent drain current

5. Apply RF

Bias OFF

1. Turn RF off

2. Apply pinch-off voltage to the gate

3. Turn-off drain voltage

4. Turn-off gate voltage