PPC5567MZP80R2 datasheet(44/56 Pages) FREESCALE

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MPC5567 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Electrical Characteristics

Freescale Semiconductor

3.13.9

eQADC SSI Timing

Figure 27. EQADC SSI Timing

Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V) 1

1 SS timing specified at F

SYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,

TA = TL to TH, and CL = 50pF with SRC = 0b11.

CLOAD = 25pF on all outputs. Pad drive strength set to maximum.

Num

Rating

Symbol

Min

Typ

Max

Unit

FCK Frequency 2, 3

2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.

3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.

fFCK

1/17

—

/2f

SYS_CLK

2FCK Period (tFCK = 1/ fFCK)

tFCK

2—

tSYS_CLK

Clock (FCK) High Time

tFCKHT

tSYS_CLK − 6.5

—

9* tSYS_CLK + 6.5

Clock (FCK) Low Time

tFCKLT

tSYS_CLK − 6.5

—

8* tSYS_CLK + 6.5

SDS Lead/Lag Time

tSDS_LL

–7.5

—

+7.5

SDO Lead/Lag Time

tSDO_LL

–7.5

—

+7.5

EQADC Data Setup Time (Inputs)

tEQ_SU

—

EQADC Data Hold Time (Inputs)

tEQ_HO

1—

—

1st (MSB)

2nd

25th

26th

1st (MSB) 2nd

25th

26th

FCK

SDS

SDO

External Device Data Sample at

SDI

EQADC Data Sample at

FCK Falling Edge

FCK Rising Edge

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