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PPC5567MZP80R2 数据表(PDF) 47 Page - Freescale Semiconductor, Inc |
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PPC5567MZP80R2 数据表(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 56 page ![]() Electrical Characteristics MPC5567 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Freescale Semiconductor 47 3.14.3 MII Async Inputs Signal Timing (CRS and COL) Table 30 lists MII asynchronous inputs signal timing. Figure 30 shows MII asynchronous input timings listed in Table 30. Figure 30. MII Async Inputs Timing Diagram 3.14.4 MII Serial Management Channel Timing (MDIO and MDC) Table 31 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Figure 31 shows MII serial management channel timings listed in Table 31. Table 30. MII Async Inputs Signal Timing Num Characteristic Min Max Unit 9 CRS, COL minimum pulse width 1.5 — TX_CLK period Table 31. MII Serial Management Channel Timing Num Characteristic Min Max Unit 10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0 — ns 11 MDC falling edge to MDIO output valid (max prop delay) — 25 ns 12 MDIO (input) to MDC rising edge setup 10 — ns 13 MDIO (input) to MDC rising edge hold 0 — ns 14 MDC pulse width high 40% 60% MDC period 15 MDC pulse width low 40% 60% MDC period CRS, COL M9 |
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