Nexperia

74ALVT16821

20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state

74ALVT16821

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Product data sheet

Rev. 4 — 22 January 2018

9 / 16

Symbol Parameter

Conditions

Min

Typ[1]

Max

Unit

VCC = 3.3 V ± 0.3 V

tPLH

LOW to HIGH propagation delay

nCP to nQn; see Figure 5

0.5

1.7

3.0

ns

tPHL

HIGH to LOW propagation delay

nCP to nQn; see Figure 5

0.5

1.8

3.2

ns

tPZH

OFF-state to HIGH propagation delay

nOE to nQn; see Figure 7

1.0

2.1

3.5

ns

tPZL

OFF-state to LOW propagation delay

nOE to nQn; see Figure 7

0.5

1.4

3.0

ns

tPHZ

HIGH to OFF-state propagation delay

nOE to nQn; see Figure 7

1.5

2.9

4.2

ns

tPLZ

LOW to OFF-state propagation delay

nOE to nQn; see Figure 7

1.5

2.4

3.4

ns

nDn to nCP; HIGH; see Figure 6

1.5

0.1

-

ns

tsu

set-up time

nDn to nCP; LOW; see Figure 6

1.5

0.1

-

ns

nDn to nCP; HIGH; see Figure 6

0.5

0.1

-

ns

th

hold time

nDn to nCP; LOW; see Figure 6

0.5

0.1

-

ns

nCP HIGH; see Figure 5

1.5

-

-

ns

tW

pulse width

nCP LOW

1.5

-

-

ns

fmax

maximum frequency

nCP; see Figure 5

150

-

-

MHz

[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.

All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.

10.1 Waveforms and test circuit

001aaa256

nCP input

nQn output

tPHL

tPLH

tW

VOH

VI

GND

VOL

VM

VM

VM

1/fmax

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 5. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock

frequency