Nexperia

74ALVT16821

20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state

74ALVT16821

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© Nexperia B.V. 2018. All rights reserved.

Product data sheet

Rev. 4 — 22 January 2018

2 / 16

3 Ordering information

Table 1. Ordering information

Package

Type number

Temperature range

Name

Description

Version

74ALVT16821DGG

-40 °C to +85 °C

TSSOP56 plastic thin shrink small outline package;

56 leads; body width 6.1 mm

SOT364-1

4 Functional diagram

001aad153

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9

42 41 40 38 37 36 34 33 31 30

15 16 17 19 20 21 23 24 26 27

28

2OE

29

2CP

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9

55 54 52 51 49 48 47 45 44 43

2

3

5

6

8

9

10 12 13 14

1

1OE

56

1CP

Figure 1. Logic symbol

29

28

56

EN4

1

EN2

1OE

1CP

2OE

2CP

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1D9

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2D9

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

1Q9

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

2Q9

C3

C1

2

1D

3D

4

001aad155

42

41

40

38

37

36

34

33

31

30

15

16

17

19

20

21

23

24

26

27

55

54

52

51

49

48

47

45

44

43

2

3

5

6

8

9

10

12

13

14

Figure 2. IEC logic symbol

001aad156

D

CP Q

nD2

nCP

nOE

nQ2

D

CP Q

nD3

nQ3

D

CP Q

nD4

D

CP Q

nD0

nQ0

D

CP Q

nD1

nQ1

nQ4

D

CP Q

nD5

nQ5

D

CP Q

nD6

nQ6

D

CP Q

nD7

nQ7

D

CP Q

nD8

nQ8

D

CP Q

nD9

nQ9

Figure 3. Logic diagram