8.

Read Operations

Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in

the device address byte must be a logic ‘1’. There are four read operations:

• Current Address Read

• Random Address Read

• Sequential Read

• Serial Number Read

Note:  The AT24CS32 contains a single Address Pointer register, which is shared by both the EEPROM and the

serial number. As such, when changing from one region to the other, the first read operation in the new region should

begin with a dummy write sequence (i.e., a random read operation with the new region’s device address and word

address bytes) in order to ensure the Address Pointer is set to a known value. See Serial Number Read for additional

requirements on the serial number read.

8.1

Current Address Read

The internal data word address counter maintains the last address accessed during the last read or write operation,

incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The

address rollover during a read is from the last byte of the last page to the first byte of the first page of the memory.

A current address read operation will output data according to the location of the internal data word address counter.

This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The

device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types of

read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a

Start condition to begin the next sequence.

Figure 8-1. Current Address Read

SCL

SDA

Device Address Byte

Data Word (n)

Start Condition

by Master

ACK

from Slave

NACK

from Master

Stop Condition

by Master

MSb

MSb

1

0

1

0

A

2

A

1

A

0

1

0

D7 D6

D5 D4 D3

D2 D1 D0

1

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

8.2

Random Read

A random read begins in the same way as a byte write operation does to load in a new data word address. This is

known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted

to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in

and acknowledged by the EEPROM, the bus master must generate another Start condition. The bus master now

initiates a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit

set to logic ‘1’. The EEPROM will ACK the device address and serially clock out the data word on the SDA line. All

types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the

ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can

send a Start condition to begin the next sequence.

AT24CS32

Read Operations

© 2020 Microchip Technology Inc.

Datasheet

DS20006341A-page 21