Preliminary Product Information U18551EJ2V0PM

5

µ PD78F9210CS, 78F9211CS, 78F9212CS

BLOCK DIAGRAM

78K0S

CPU

CORE

INTERNAL

HIGH-SPEED

RAM

FLASH

MEMORY

VSSNote2

VDDNote1

PORT 2

P20-P23

4

POWER ON CLEAR/

LOW VOLTAGE

INDICATOR

POC/LVI

CONTROL

RESET CONTROL

SYSTEM

CONTROL

HIGH-SPEED

INTERNAL

OSCILLATOR

RESET/P34

X1/P23

X2/P22

16-bit TIMER/

EVENT COUNTER 00

TO00/TI010/P21

TI000/P20

TOH1/P20

8-bit TIMER H1

INTP0/P21

INTP1/P32

ANI0/P20-

ANI3/P23

4

A/D CONVERTER

INTERRUPT

CONTROL

PORT 3

P32

P34

PORT 4

P40-P47

8

LOW-SPEED

INTERNAL

OSCILLATOR

WATCHDOG TIMER

Notes 1. In the

µPD78F9210CS, 78F9211CS, 78F9212CS, VDD functions alternately as the A/D converter reference

voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).

2. In the

µPD78F9210CS, 78F9211CS, 78F9212CS, VSS functions alternately as the ground potential of the

A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V).