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UPD78F9211CS 数据表(PDF) 21 Page - Renesas Technology Corp

部件名 UPD78F9211CS
功能描述  MOS INTEGRATED CIRCUIT
PDF  30 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD78F9211CS 数据表(HTML) 21 Page - Renesas Technology Corp

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Preliminary Product Information U18551EJ2V0PM
19
µ PD78F9210CS, 78F9211CS, 78F9212CS
A/D Converter Characteristics (TA =
−40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 VNote 1, VSS = 0 VNote 2)
(1) A/D converter basic characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
10
10
bit
4.5 V
≤ VDD ≤ 5.5 V
3.0
100
µs
4.0 V
≤ VDD < 4.5 V
4.8
100
µs
2.85 V
≤ VDD < 4.0 V
6.0
100
µs
Conversion time
tCONV
2.7 V
≤ VDD < 2.85 V
14.0
100
µs
Analog input voltage
VAIN
VSS
Note 2
VDD
V
(2) A/D Converter Characteristics (high-speed internal oscillation clock)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Overall error
Notes 3, 4
AINL
−0.1 to +0.2Note 5 −0.35 to +0.45
%FSR
Zero-scale error
Notes 3, 4
Ezs
−0.1 to +0.2Note 5 −0.35 to +0.45
%FSR
Full-scale error
Notes 3, 4
Efs
−0.1 to +0.2Note 5 −0.35 to +0.40
%FSR
Integral non-linearity error
Note 3
ILE
±1Note 5
±3
LSB
Differential non-linearity error
Note 3
DLE
±1Note 5
±1.5
LSB
(3) A/D Converter Characteristics (Crystal/Ceramic Oscillation Clock, External Clock)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V
≤ VDD ≤ 5.5 V
−0.20 to +0.35Note 5 −0.35 to +0.65
%FSR
Overall error
Notes 1, 2
AINL
2.7 V
≤ VDD < 4.0 V
±0.25Note 5
−0.35 to +0.55
%FSR
4.0 V
≤ VDD ≤ 5.5 V
−0.20 to +0.35Note 5 −0.35 to +0.65
%FSR
Zero-scale error
Notes 3, 4
Ezs
2.7 V
≤ VDD < 4.0 V
±0.25Note 5
−0.35 to +0.55
%FSR
4.0 V
≤ VDD ≤ 5.5 V
−0.20 to +0.35Note 5 −0.35 to +0.55
%FSR
Full-scale error
Notes 3, 4
Efs
2.7 V
≤ VDD < 4.0 V
±0.25Note 5
−0.35 to +0.50
%FSR
4.0 V
≤ VDD ≤ 5.5 V
±1.5Note 5
±3.0
LSB
Integral non-linearity error
Note 3
ILE
2.7 V
≤ VDD < 4.0 V
±1.5Note 5
±4.0
LSB
4.0 V
≤ VDD ≤ 5.5 V
±1.0Note 5
±2.5
LSB
Differential non-linearity error
Note 3
DLE
2.7 V
≤ VDD < 4.0 V
±1.0Note 5
±2.5
LSB
Notes 1.
In the 78K0S/KY1+, VDD functions alternately as the A/D converter reference voltage input. When using
the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2.
In the 78K0S/KY1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
3.
Excludes quantization error (
±1/2 LSB).
4.
This value is indicated as a ratio (%FSR) to the full-scale value.
5.
A value when HALT mode is set by an instruction immediately after A/D conversion starts.
Caution The conversion accuracy may be degraded if the level of a port that is not used for A/D conversion
is changed during A/D conversion.



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