UPD6708 datasheet(67/74 Pages) RENESAS

67 / 74 page

µPD6708

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

System clock

fX = 12 MHz

Using communication mode 2

11.94

12.00

12.06

MHz

Using communication mode 0,1

11.82

12.00

12.18

MHz

fX = 12.58 MHz

Using communication mode 2

12.52

12.58

12.64

MHz

Using communication mode 0,1

12.40

12.58

12.76

MHz

SCK cycle time

tKCY

0.8

µs

SCK high-level width

tKH

0.4

µs

SCK low-level width

tKL

0.4

µs

SI setup time (to SCK

↑)tSIK

100

SI hold time (from SCK

↑)tKSI

400

SO output delay time (from SCK

↑)

tKSO

300

CS, C/D, R/W setup time (to SCK

↑)

tSA

0ns

CS, C/D, R/W hold time (from SCK

↑)

tHA

400

CS high-level width

400

IRQ output high-level width

µs

RESET low-level width

µs

Oscillation stabilization time

tOS

fX = 12 MHz

AC Characteristics (TA = –40 to +85

°C, VDD = AVDD = 5 V ±10 %)

Serial Transfer Timing

CS, C/D, R/W

SCK

tSA

tHA

tKYC

tKL

tKH

tSIK

tKSI

Data Input

Data Output

tKSO

UPD6708 数据表(PDF) 67 Page - Renesas Technology Corp

UPD6708 数据表(HTML) 67 Page - Renesas Technology Corp

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