3

Electrical Data

3.1

Absolute maximum ratings

Table 2. Absolute maximum ratings

each voltage referred to GND unless otherwise specified

Symbol

Parameter

Test Condition

Value

Unit

VDS

GaN Drain-to-Source Voltage

TJ = 25 °C

620

V

VCC

Logic supply voltage

-0.3 to 11

V

PVCC-PGND Low-side driver supply voltage (1)

-0.3 to 7

V

VCC-PGND

Logic supply vs. Low-side driver ground

-0.3 to 18.3

V

PVCC

Low-side driver supply vs. logic ground

-0.3 to 18.3

V

PGND

Low-side driver ground vs. logic ground

-7.3 to 11.3

V

VBO

BOOT to OUTb voltage (2)

-0.3 to 7

V

BOOT

Bootstrap voltage

-0.3 to 620

V

CGL, CGH

Maximum external capacitance between GL and PGND and

between GH and OUTb

Fsw = 500 kHz (3)

3.9

nF

RGL, RGH

Minimum external pull-down resistance between GL and

PGND and GH and OUTb

6.8

kΩ

ID

Drain current (Low side GaN transistor)

DC @ TCB = 25°C (4) (5)

9.7

A

DC @ TCB = 100°C(4) (5)

6.4

A

Peak @ TCB = 25°C(4) (5) (6)

17

A

ID

Drain current (High side GaN transistor)

DC @ TCB = 25°C (4) (5)

6.5

A

DC @ TCB = 100°C(4) (5)

4.4

A

Peak @ TCB = 25°C(4) (5) (6)

12

A

SRout

Half-bridge outputs slew rate (10% - 90%)

100

V/ns

Vi

Logic inputs voltage range

-0.3 to 21

V

TJ

Junction temperature

-40 to 150

°C

Ts

Storage temperature

-40 to 150

°C

1. PGND internally connected to SENSE

2. OUTb internally connected to OUT

3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12)

4. TCB is temperature of case exposed pad.

5. Range estimated by characterization, not tested in production.

6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.

MASTERGAN2

Electrical Data

DS13597 - Rev 2.0

page 4/29