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DIX4192IPFBT 数据表(PDF) 3 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
部件名 DIX4192IPFBT
功能描述  Integrated Digital Audio Interface Receiver and Transmitter
PDF  60 Pages
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制造商  BURR-BROWN [Burr-Brown (TI)]
网页  http://www.burr-brown.com
标志 BURR-BROWN - Burr-Brown (TI)

DIX4192IPFBT 数据表(HTML) 3 Page - Burr-Brown (TI)

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ELECTRICAL CHARACTERISTICS: General, DIR, and DIT
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
DIX4192
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL I/O CHARACTERISTICS
(All I/O pins except line receivers and line driver)
High-level input voltage, VIH
0.7 × VIO
VIO
V
Low-level input voltage, VIL
0
0.3 × VIO
V
High-level input current, IIH
0.5
10
µA
Low-level input current, VIL
0.5
10
µA
High-level output voltage, VOH
IO = –4mA
0.8 × VIO
VIO
V
Low-level output voltage, VOL
IO = +4mA
0
0.2 × VIO
V
Input capacitance, CIN
3
pF
LINE RECEIVER INPUTS
(RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)
Voltage across a given
Differential input sensitivity, VTH
150
200
mV
differential input pair
Input hysteresis, VHY
150
mV
LINE DRIVER OUTPUTS
(TX+, TX–)
Differential output voltage, VTXO
RL = 110Ω Across TX+ and TX–
5.4
VPP
MASTER CLOCK INPUT
Master clock input (MCLK) frequency, fMCLK
1
27.7
MHz
Master clock input (MCLK) duty cycle, fMCLKD
45
55
%
DIGITAL AUDIO INTERFACE RECEIVER (DIR)
PLL lock range
20
216
kHz
Reference clock input (RXCKI) frequency, fRXCKI
3.5
27.7
MHz
Reference clock input (RXCKI) duty cycle, fRXCKID
45
55
%
Recovered clock output (RXCKO) frequency, fRXCKO
3.5
27.7
MHz
Recovered clock output (RXCKO) duty cycle, fRXCKOD
45
55
%
Recovered clock output (RXCKO) intrinsic jitter
Measured cycle-to-cycle
250
ps RMS
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
Intrinsic output jitter
Measured cycle-to-cycle
200
ps RMS
3
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