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DIX4192

SBFS031C – JANUARY 2006 – REVISED JUNE 2006

Register 03: Port A Control Register 1

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

0

AMUTE

AOUTS1

AOUTS0

AM/S

AFMT2

AFMT1

AFMT0

AFMT[2:0]

Port A Audio Data Format

These bits are used to set the audio input and output data format for Port A. Refer to the Audio Serial Port Operation section for

illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable

timing diagram and parameters.

AFMT2

AFMT1

AFMT0

Audio Data Format

0

0

0

24-Bit Left-Justified (default)

0

1

0

0

1

0

Unused

0

1

1

Unused

1

0

0

16-Bit Right-Justified

1

0

1

18-Bit Right-Justified

1

1

0

20-Bit Right-Justified

1

1

1

24-Bit Right-Justified

AM/S

Port A Slave/Master Mode

This bit is used to set the audio clock mode for Port A to either Slave or Master.

AM/S

Slave/Master Mode

0

Slave mode; the LRCK and BCK clocks are inputs generated by an external digital audio source. (default)

1

Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source.

AOUTS[1:0]

Port A Output Data Source

These bits are used to select the output data source for Port A. The data is output at SDOUTA (pin 40).

AOUTS1

AOUTS0

Output Data Source

0

0

Port A input, for data loop back. (default)

0

1

Port B input

1

0

DIR

1

1

Reserved

AMUTE

Port A Output Mute

This bit is used to mute the Port A audio data output.

AMUTE

Output Mute

0

Disabled; SDOUTA is driven by the output data source. (default)

1

Enabled; SDOUTA is forced low.

Register 04: Port A Control Register 2

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

0

0

0

0

ACLK1

ACLK0

ADIV1

ADIV0

ADIV[1:0]

Port A Master Clock Divider

These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation.

BCKA is always set to 64 times the LRCKA clock rate in Master mode.

ADIV1

ADIV0

Master Mode Clock Divider

0

0

Divide-by-128 (default)

0

1

Divide-by-256

1

0

Divide-by-384

1

1

Divide-by-512

36

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