ST7L19 datasheet(22/138 Pages) STMICROELECTRONICS

22 / 138 page

ST7L15, ST7L19

22/138

SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1 MHz frequen-

cy from the RC oscillator or the external clock by 4

or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena-

bled and the multiplication factor of 4 or 8 is select-

ed by 2 option bits:

– The x4 PLL is intended for operation with VDD in

the 3V to 3.6V range (available only on Flash de-

vices)

– The x8 PLL is intended for operation with VDD in

the 3.6V to 5.5V range1)

Refer to Section 15.1 for the option byte descrip-

tion.

If the PLL is disabled and the RC oscillator is ena-

bled, then fOSC =1MHz.

If both the RC oscillator and the PLL are disabled,

fOSC is driven by the external clock.

Figure 11. PLL Output Frequency Timing

Diagram

When the PLL is started, after reset or wake-up

from HALT mode or AWUFH mode, it outputs the

clock after a delay of tSTARTUP.

When the PLL output signal reaches the operating

frequency, the LOCKED bit in the SICSCR register

is set. Full PLL accuracy (ACCPLL) is reached after

a stabilization time of tSTAB (see Figure 11 and

section 13.3.3 on page 105)

Refer to section 7.6.3 on page 30 for a description

of the LOCKED bit in the SICSR register.

Note:

1. It is possible to obtain fOSC = 4 MHz in the 3.3V

to 5.5V range with internal RC and PLL enabled by

selecting 1 MHz RC and x8 PLL and setting the

PLLdiv2 bit in the PLLTST register (see section

7.6.3 on page 30).

7.3 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER

(MCCSR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by

hardware after a reset. This bit enables the MCO

output clock.

0: MCO clock disabled, I/O port free for general

purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow Mode select

This bit is read/write by software and cleared by

hardware after a reset. This bit selects the input

clock fOSC or fOSC/32.

0: Normal mode (fCPU = fOSC)

1: Slow mode (fCPU = fOSC/32)

RC CONTROL REGISTER (RCCR)

Read / Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-

justment Bits

These bits must be written immediately after reset

to adjust the RC oscillator frequency and to obtain

an accuracy of 1%. The application can store the

correct value for each voltage range in EEPROM

and write it to this register at start-up.

00h = maximum available frequency

FFh = lowest available frequency

These bits are used with the CR[1:0] bits in the

SICSR register. Refer to section 7.6.3 on page 30.

Note: To tune the oscillator, write a series of differ-

ent values in the register until the correct frequen-

cy is reached. The fastest method is to use a di-

chotomy starting with 80h.

4/8 x

freq.

LOCKED bit set

tSTAB

tLOCK

input

tSTARTUP

000

MCO

SMS

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

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