Si53112

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

13

Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 2, 2021

2.5.1. PWRDN Assertion

When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held

LOW/LOW on the next DIF high-to-low transition.

Figure 1. PWRDN Assertion

2.5.2. PWRGD Assertion

The power-up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion

of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs

stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN

deassertion to a voltage greater than 200 mV.

Figure 2. PWRDG Assertion (Pwrdown—Deassertion)

PWRDWN

DIF

DIF

Tstable

<1.8 ms

Tdrive_Pwrdn#

<300 µs; > 200 mV

DIF

DIF

PWRDWN