Si53112

20

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 2, 2021

4.3. Control Registers

Note: Byte 0, bit_[3:1] are BW PLL SW enable for the DB1200ZL. Setting bit 3 to 1 allows the user to override the Latch value

from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode Readback Table. Note that Bits 7 and 6

will keep the value originally latched on pin 5. A warm reset of the system will have to be accomplished if the user

changes these bits.

Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register

Bit

Description

If Bit = 0

If Bit = 1

Type

Default

Output(s)

Affected

0

100M_133M#

Frequency Select

133 MHz

100 MHz

R

Latched at

power up

DIF[11:0]

1

PLL Mode 0

See PLL Operating Mode

Readback Table

RW

1

2

PLL Mode 1

RW

1

3

PLL Software Enable

HW Latch

SMBUS

Control

RW

0

4

Reserved

0

5

Reserved

0

6

PLL Mode 0

See PLL Operating Mode

Readback Table

R

Latched at

power up

7

PLL Mode 1

See PLL Operating Mode

Readback Table

R

Latched at

power up