| 数据搜索系统,热门电子元器件搜索 |
|
SI53112-A00AGMR 数据表(PDF) 27 Page - Skyworks Solutions Inc. |
|
|
|||||||||||||||||||||||||||||
SI53112-A00AGMR 数据表(HTML) 27 Page - Skyworks Solutions Inc. |
|
27 / 35 page ![]() Si53112 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 27 Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 2, 2021 Table 25. Si53112 64-Pin QFN Descriptions Pin # Name Type Description 1VDDA 3.3 V 3.3 V power supply for PLL. 2 GNDA GND Ground for PLL. 3NC I/O No connect. 4 100M_133M I,SE 3.3 V tolerant inputs for input/output frequency selection. An external pull- up or pull-down resistor is attached to this pin to select the input/output frequency. High = 100 MHz output Low = 133 MHz output 5 HBW_BYPASS_LBW I, SE Tri-Level input for selecting the PLL bandwidth or bypass mode. High = High BW mode Med = Bypass mode Low = Low BW mode 6 PWRGD/PWRDN I 3.3 V LVTTL input to power up or power down the device. 7GND GND Ground for outputs. 8 VDDR VDD 3.3 V power supply for differential input receiver. This VDDR should be treated as an analog power rail and filtered appropriately. 9 CLK_IN I, DIF 0.7 V Differential input. 10 CLK_IN I, DIF 0.7 V Differential input. 11 SA_0 I 3.3 V LVTTL input selecting the address. Tri-level input. 12 SDA I/O Open collector SMBus data. 13 SCL I/O SMBus slave clock input. 14 SA_1 I 3.3 V LVTTL input selecting the address. Tri-level input. 15 NC I/O No connect. There are active signals on pin 15 and 16, do not connect anything to these pins. 16 NC I/O No connect. There are active signals on pin 15 and 16, do not connect anything to these pins. 17 DIF_0 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 18 DIF_0 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 19 OE_0 I, SE 3.3 V LVTTL active low input for enabling differential outputs (default). Controls the corresponding output pair. Internal pull-down. 20 OE_1 I, SE 3.3 V LVTTL active low input for enabling differential outputs (default). Controls the corresponding output pair. Internal pull-down. 21 DIF_1 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 22 DIF_1 O, DIF 0.7 V Differential clock outputs. Default is 1:1. 23 GND GND Ground for outputs. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |