Si53112

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Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 2, 2021

2. Functional Description

2.1. CLK_IN, CLK_IN

The differential input clock is expected to be sourced from a clock synthesizer, e.g. CK420BQ, CK509B, or CK410B+.

2.2. OE and Output Enables (Control Registers)

Each output can be individually enabled or disabled by SMBus control register bits. Additionally, each output of the

DIF[11:0] has a dedicated OE pin. The OE pins are asynchronous, asserted-low signals. The Output Enable bits in

the SMBus registers are active high and are set to enable by default. The disabled state for the DB1200ZL NMOS

push-pull output is Low/Low. Please note that the logic level for assertion or deassertion is different in software

than it is on hardware. This follows hardware default nomenclature for communication channels (e.g., output is

enabled if the OE# pin is pulled low) and still maintains software programming logic (e.g., output is enabled if OE

register is true). Table 9 is a truth table depicting enabling and disabling of outputs via hardware and software. Note

that, for the output to be active, the control register bit must be a 1 and the OE pin must be a 0.

Note: The assertion and deassertion of this signal is absolutely asynchronous.

2.2.1. OE Assertion (Transition from 1 to 0)

All differential outputs that were disabled are to resume normal operation in a glitch-free manner. The latency from

the assertion to active outputs is 4 to 12 DIF clock periods.

2.2.2. OE De-Assertion (Transition from 0 to 1)

The impact of deasserting OE is that each corresponding output will transition from normal operation to disabled in

a glitch-free manner. A minimum of four valid clocks will be provided after the deassertion of OE. The maximum

latency from the deassertion to disabled outputs is 12 DIF clock periods.

2.3. 100M_133M—Frequency Selection

The Si53112 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.

100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.

Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53112 is operated in 1:1

mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-down

resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 10.

Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch-free manner.

Table 9. Si53112 Output Management

Inputs

OE Hardware Pins and Control Register Bits

Outputs

PLL State

PWRGD/PWR

DN

CLK_IN/CLK_

IN

SMBUS

Enable Bit

OE Pin

DIF/DIF[11:0] FB_OUT/FB_

OUT

0

x

x

x

Low/Low

Low/Low

OFF

1

Running

0

x

Low/Low

Running

ON

1

0

Running

Running

ON

1

1

Low/Low

Running

ON

Table 10. Frequency Program Table

100M_133M

Optimized Frequency (CLK_IN = CLK_OUT)

0133.33 MHz

1100.00 MHz