Si53112

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Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 2, 2021

2.8. Buffer Power-Up State Machine

Figure 3. Buffer Power-Up State Diagram

Table 14. Buffer Power-Up State Machine

State

Description

0

3.3 V buffer power is off.

1

After 3.3 V supply is detected to rise above 1.8–2.0 V, the

buffer enters State 1 and initiates a 0.1–0.3 ms delay.

2

Buffer waits for a valid clock on the CLK input and PWRDN

de-assertion.

3

Once the PLL is locked to the CLK_IN input clock, the buffer

enters state 3 and enables outputs for normal operation.

Notes:

1. The total power-up latency from power-on to all outputs active must be less

than 1.8 ms (assuming a valid clock is present on CLK_IN input).

2. If power is valid and power-down is deasserted but no input clocks are

present on the CLK_IN input, DIF clocks must remain disabled. Only after

valid input clocks are detected, valid power, PWRDN deasserted with the

PLL locked/stable are the DIF outputs enabled.

Power Off

S0

Normal

Operation

S3

Powerdown Asserted

Delay

0.1 ms – 0.3 ms

S1

Wait for input

clock and

powerdown

deassertion

S2

No input clock