DA9078.003

28 January 2004

5 (10)

SAMPLES IN SBDIL 20 PACKAGE

PIN DESCRIPTION

Pin Name

Pin

Type

Function

Note

NC

1

VDD

2

P

Positive Power Supply

NC

3

QO

4

AO

Quartz Filter Output

NC

5

1

QI

6

AI

Quartz Filter Input

AGC

7

AO

AGC Capacitor

OUT

8

DO

Receiver Output

2

NC

9

NC

10

NC

11

NC

12

NC

13

NC

14

DEC

15

AO

Demodulator Capacitor

AON

16

DI

AGC On Control

3

PDN

17

AI

Power Down Input

4

RFI

18

AI

Receiver Input

NC

19

VSS

20

G

Power Supply Ground

Notes:

1) Pin 5 between quartz crystal filter pins must be connected to VSS to eliminate DIL package leadframe

parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also

recommended to be connected to VSS to minimize noise coupling.

2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced

(modulated)

-

-

at power down the output is pulled to VSS (pull down switch)

3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)

-

Internal pull-up with current < 1

µA which is switched off at power down

4) PDN = VSS means receiver on; PDN = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up

(PDN=VSS) i.e. at the falling edge of PDN signal.

NC 1

VDD 2

NC 3

QO 4

NC 5

QI 6

AGC 7

OUT 8

NC 9

NC 10

20 VSS

19 NC

18 RFI

17 PDN

16 AON

15 DEC

14 NC

13 NC

12 NC

11 NC

Top Marking Definitions:

YYWW = Year Week

XXXXX.X = Lot Number