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DA9187.002

29 January, 2004

OPERATING MODES

DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)

(note: VREFL=GND in case of MAS9187A1). XRESET pin is used for middle code preset: DAC registers are

reset and middle code will appear at the DAC output.

Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.

Rising XCS-pin stops data reading and 12 CLK-cycles are used as the input data (4 address bits and 8 data

bits). The last 12 bits before rising XCS are used as input data.

◆ Timing diagram

APPLICATION AND TEST CIRCUIT INFORMATION

Clock

Data In

MAS9187A2

O8

O1

O2

O3

O4

O5

O6

O7

15

14

7

6

5

4

3

2

VREFH

VREFL

CLK

SDI

12

13

Controller

O12

O9

O10

O11

19

18

17

16

VDD

GND

+3.0v

11

10

1

20

XCS

Latch

9

8

XSHDN

100 nF

SDI

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

CLK

XCS

DAC Register Load

V

OUT