CSTS0200MGA06 datasheet(43/153 Pages) STMICROELECTRONICS

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ST72334J/N, ST72314J/N, ST72124J

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I/O PORTS (Cont’d)

12.4 LOW POWER MODES

12.5 INTERRUPTS

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and the I-bit in the CC reg-

ister is reset (RIM instruction).

Table 8. Port Configuration

Mode

Description

WAIT

No effect on I/O ports. External interrupts

cause the device to exit from WAIT mode.

HALT

No effect on I/O ports. External interrupts

cause the device to exit from HALT mode.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on

selected external

event

DDRx

ORx

Yes

Port

Pin name

Input

Output

OR = 0

OR = 1

OR = 0

OR = 1

High-Sink

Port A

PA7:6

floating

true open-drain

Yes

PA5:4

floating

pull-up

open drain

push-pull

PA3

floating

floating interrupt

open drain

push-pull

PA2:0

floating

pull-up interrupt

open drain

push-pull

Port B

PB4:3

floating

floating interrupt

open drain

push-pull

PB7:5, PB2:0

floating

pull-up interrupt

open drain

push-pull

Port C

PC7:4, PC1:0

floating

pull-up

open drain

push-pull

PC3:2

floating

pull-up

open drain

push-pull

Yes

Port D

PD7:0

floating

pull-up

open drain

push-pull

Port E

PE7:4

floating

pull-up

open drain

push-pull

Yes

PE1:0

floating

pull-up

open drain

push-pull

Port F

PF7:6

floating

pull-up

open drain

push-pull

Yes

PF4

floating

pull-up

open drain

push-pull

PF2

floating

floating interrupt

open drain

push-pull

PF1:0

floating

pull-up interrupt

open drain

push-pull

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