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CSTS0200MGA06 数据表(PDF) 48 Page - STMicroelectronics |
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CSTS0200MGA06 数据表(HTML) 48 Page - STMicroelectronics |
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48 / 153 page ![]() ST72334J/N, ST72314J/N, ST72124J 48/153 MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read /Write Reset Value: 0000 0000 (00h) Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability. The beep output signal is available in ACTIVE- HALT mode but has to be disabled to reduce the consumption. Bit 3:2 = Reserved Must always be cleared Bit 1 = SSM SS mode selection It is set and cleared by software. 0: Normal mode - SS uses information coming from the SS pin of the SPI. 1: I/O mode, the SPI uses the information stored into bit SSI. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software. Table 10. Miscellaneous Register Map and Reset Values 70 - - BC1 BC0 - - SSM SSI Beep mode with fOSC=16MHz BC1 BC0 Off 0 0 ~2-KHz Output Beep signal ~50% duty cycle 01 ~1-KHz 1 0 ~500-Hz 1 1 Address (Hex.) Register Label 76 54321 0 0020h MISCR1 Reset Value IS11 0 IS10 0 MCO 0 IS21 0 IS20 0 CP1 0 CP0 0 SMS 0 0040h MISCR2 Reset Value 0 0 BC1 0 BC0 000 SSM 0 SSI 0 |
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