RT6310ASLASHAH datasheet(4/54 Pages) RICHTEK

4 / 54 page

RT6310

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS6310-04

August 2023

Functional Pin Description

Pin No.

Pin Name

Pin Function

BOOT

Bootstrap supply for high-side gate driver. Connect a high quality and low ESR

ceramic capacitor (minimum C = 0.1

F/0603) from BOOT pin to LX pin through a

short and low inductance paths. During the period of low-side MOSFET turn-on,

the bootstrap capacitor is charged by BOOT pin to store required energy for high-

side gate driver. A bootstrap resistor (0603 size,

 10) in series with the bootstrap

capacitor is strongly recommended for reducing the voltage spike at LX node.

2, 3

Switch node of the buck converter is internally connected to the source terminal of

the high-side MOSFET and the drain terminal of the low-side MOSFET. LX is also

used for the internal ramp generation, on-time generation and current detection.

Connect this pin to output inductor and keep the sensitive trace and signals away.

4 to 14

PGND

Ground return from low-side power MOSFET and its driver. Directly soldering to a

large PCB PGND plane and connecting thermal vias under PGND pin are required

to minimize the parasitic impedance and thermal resistance.

15, 16

VIN

Input voltage pin. VIN pin is used to supply the internal bias voltage, VCC and LDO.

Use wide PCB traces and multiple vias to make the connection. Apply at least two

layers for the input trace. Connecting the ceramic capacitor (C = 10

F/0805x2 +

0.1

F/0603x1) as close as possible from VIN pin to PGND pin is necessary.

EN/MODE

(RT6310A/AH)

(RT6310B/BH)

(RT6310C/CH)

Enable and operation mode control input. In order to ensure the IC logic status of

turn-on/off, the low logic time length of EN/MODE control signal must be larger than

0.5

s. DO NOT leave this pin floating. RT6310 supports either in diode emulation

mode (DEM) or ultrasonic mode (USM) at light load (Table 1) through setting the

voltage of the EN/MODE pin. Regarding the EN/MODE control logic of RT6310,

please refer to Table 2.

EN/MODE

(RT6310D/DH)

Enable input. In order to ensure the IC logic status of turn-on/off, the low logic time

length of EN/MODE control signal must be larger than 0.5

s. DO NOT leave this

pin floating.

PGOOD

Power good indicator is an open-drain output. This pin is pulled low as UVP, OVP,

OTP, EN/MODE low or output voltage is not regulated (such as before soft-start).

An external pull-up resistor to VCC or other external rail is required, and the

recommended pull-up resistor ranges from 10k

 to 100k. Do not pull the PGOOD

voltage higher than 6V.

AGND

Ground of internal analog circuitry. AGND must be connected to the PGND plane

through a single point.

VCC

Internal LDO output. Used as supply to internal control circuits. DO NOT connect

to any external loads. Connect a high-quality capacitor (C = 1

F/0603) from this

pin to AGND. When the voltage on VCC_EXT (RT6310A/AH/B/BH/D/DH) or VOUT

(RT6310C/CH) pin is higher than "VCC bypass switch turn-on voltage", the VCC

will be internally switchover to VCC_EXT (or VOUT) to reduce power consumption

(refer to Figure 4 and Figure 5).

RT6310A/AH 数据表(PDF) 4 Page - Richtek Technology Corporation

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