RT6310ASLASHAH datasheet(41/54 Pages) RICHTEK

41 / 54 page

RT6310

is a registered trademark of Richtek Technology Corporation.

DS6310-04

August 2023

www.richtek.com

OUT



MAX

OFF_MIN

+ t

The worst-case output sag voltage is determined by :

(

)

L_PEAK

OUT_SAG

OUT

MAX

OUT

2 C







−

When the load is removed, the amount of overshoot due

to stored inductor energy is calculated as :

L_PEAK

OUT_SOAR

OUT

2 C







Ceramic capacitors have very low equivalent series

resistance

(ESR)

and

provide

the

best

ripple

performance. Be careful to consider the voltage

coefficient of ceramic capacitors when choosing the

value and case size. Most ceramic capacitors lose 50%

or more of their rated value when used near their rated

voltage.

Internal VCC Regulator (VCC)

Good bypassing at VCC pin is necessary to supply the

high transient currents required by the MOSFET gate

drivers. Place a low ESR MLCC capacitor (C =

F/0603) as close as possible to VCC pin and AGND

pin. Applications with high input voltage and high

switching frequency will increase die temperature

because of the higher power dissipation across the LDO.

Do not connect VCC pin to provide power to other

devices or loads.

External Bootstrap Capacitor and Resistor (CBOOT

and RBOOT)

Connect a 0.1

F/0603 low ESR ceramic capacitor and

 10 resistor between BOOT pin and LX pin. This

bootstrap capacitor provides the gate driver supply

voltage for the high-side MOSFET. The internal gate

driver is optimized to turn the high-side MOSFET on fast

enough for low power loss and good efficiency, but also

slow enough to reduce EMI. The most of EMI occurs

since VLX rises rapidly when the high-side MOSFET is

turned on fast. In some cases, slightly increasing the

RBOOT reduces EMI and LX pin spike directly, but the

switching loss of high-side MOSFET and die/case

temperature are also increased.

Output Voltage Programming

For the RT6310A/AH/D/DH, an external resistive divider

sets the output voltage according to the following

equation :

OUT

REF

= 1 +







VOUT

RT6310A/AH

RT6310D/DH

AGND

Figure 15. Output Voltage Setting

The recommended R2 is set to around 40k

. For a

given R2, the resistance of R1 is calculated as below :

(

)

OUT

REF

R1 =

−

1% resistors are recommended to maintain output

voltage

accuracy.

Besides,

the

resistor

divider

generates a small load on the output, which influences

the light-load efficiency. The total resistance of the FB

resistor divider should be as large as possible when

good light-load efficiency is desired.

Place resistors R1 and R2 very close to the FB pin to

minimize PCB trace length and noise. Great care should

be taken to route the FB trace away from noise sources,

such as the inductor or the LX trace. For better transient

and stability performance, it is recommended to add

CFF.

Feedforward Capacitor CFF Design

To save time for compensator design and to reduce the

layout

area

through

external

components,

the

components of compensator are integrated in the IC.

However, this integrated compensator might not be

suitable for every load transient specification. Hence, to

make

RT6310

adaptable,

the

feedforward

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