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WM8721SEDS/R 数据表(PDF) 10 Page - Wolfson Microelectronics plc

部件名 WM8721SEDS/R
功能描述  Internet Audio DAC with Integrated Headphone Driver
PDF  37 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8721SEDS/R 数据表(HTML) 10 Page - Wolfson Microelectronics plc

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WM8721 / WM8721L
Production Data
w
PD Rev 4.0 November 2004
10
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
tSCY
80
ns
SCLK pulse width low
tSCL
20
ns
SCLK pulse width high
tSCH
20
ns
SDIN to SCLK set-up time
tDSU
20
ns
SCLK to SDIN hold time
tDHO
20
ns
CSB pulse width low
tCSL
20
ns
CSB pulse width high
tCSH
20
ns
CSB rising to SCLK rising
tCSS
20
ns
SDIN
SCLK
t
3
t
1
t
6
t
2
t
7
t
5
t
4
t
3
t
8
t
10
Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
SCLK Low Pulsewidth
t1
600
ns
SCLK High Pulsewidth
t2
1.3
us
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
ns
SDIN, SCLK Rise Time
t6
300
ns
SDIN, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
600
ns
Data Hold Time
t10
900
ns



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