Production Data

WM8721 / WM8721L

w

PD Rev 4.0 November 2004

23

The exact sample rates achieved are defined by the relationships in Table 11 below.

ACTUAL SAMPLING RATE

BOSR=0

BOSR=1

TARGET

SAMPLING

RATE

MCLK=12.288

MCLK=11.2896

MCLK=18.432

MCLK=16.9344

kHz

kHz

kHz

kHz

kHz

8

8.018

8

8.018

8

(12.288MHz/256) x 1/6

(11.2896MHz/256) x 2/11

(18.432MHz/384) x 1/6

(16.9344MHz/384) x 2/11

32

32

32

(12.288MHz/256) x 2/3

not available

(18.432MHz/384) x 2/3

not available

44.1

44.1

44.1

not available

11.2896MHz/256

not available

16.9344MHz /384

48

48

48

12.288MHz/256

not available

18.432MHz/384

not available

88.2

88.2

88.2

not available

(11.2896MHz/256) x 2

not available

(16.9344MHz /384) x 2

96

96

96

(12.288MHz/256) x 2

not available

(18.432MHz/384) x 2

not available

Table 11 Normal Mode Actual Sample Rates

128/192FS NORMAL MODE

The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the

WM8721 is also capable of being clocked from a 128/192fs MCLK for application over limited

sampling rates as shown in the table below.

SAMPLING

RATE

ADC

DAC

MCLK

FREQUENCY

SAMPLE

RATE

REGISTER SETTINGS

DIGITAL

FILTER

TYPE

kHz

kHz

MHz

BOSR

SR3

SR2

SR1

SR0

6.144

0

0

1

1

1

48

48

9.216

1

0

1

1

1

2

5.6448

0

1

1

1

1

44.1

44.1

8.4672

1

1

1

1

1

2

Table 12 128/192fs Normal Mode Sample Rate Look-up Table

512/768fs NORMAL MODE

512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bir (register 8, bit 6).

The core clock to the DSP will be divided by 2 so an external 512/768fs MCLK will become 256/384

fs internally and the device otherwise operates as in Table 9 but with MCLK at twice the specified

rate.