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STR730FZ1T7 数据表(PDF) 33 Page - STMicroelectronics

部件名 STR730FZ1T7
功能描述  ARM7TDMI 32-bit MCU with Flash, 3x CAN, 4 UARTs, 20 timers, ADC, 12 comm. interfaces
PDF  53 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR730FZ1T7 数据表(HTML) 33 Page - STMicroelectronics

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STR73xF
Electrical parameters
33/53
RC/Backup Oscillator characteristics
VDD = 5V ± 10%, TA = -40°C to TAmax, unless otherwise specified.
Table 14. RC Oscillator Characteristics
1) CMU_RCCTL = 0x8
2) RC frequency shift versus average value (%)
PLL Electrical Characteristics
VDD = 5V ± 10%, TA = -40°C to TAmax, unless otherwise specified
Table 15.
PLL characteristics.
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
fRC
RC Frequency
High Frequency mode 1)
2.35
MHz
Low Frequency mode1)
29
kHz
fRCHF
RC High Frequency
CMU_RCCTL = 0x0
3
MHz
CMU_RCCTL = 0xF
2.3
MHz
fRCLF
RC Low Frequency
CMU_RCCTL = 0x0
35
kHz
CMU_RCCTL = 0xF
30
kHz
fRCHFS
2)
RC High Frequency stability
Fixed CMU_RCCTL
10
%
fRCLFS
2)
RC Low Frequency stability
Fixed CMU_RCCTL
23
%
tRCSTUP
RC Start-up Time
Stable VDD, fRC = 2.35
MHz, TA = 25
oC
2.35
µs
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
fPLLIN
(1)
1.
fPLLIN is obtained from fOSC directly or through an optional divider by 2.
2.
Typical data are based on TA=25°C, VDD=5V
3.
Max value is guaranteed by characterization, not tested in production.
PLL reference clock
FREF_RANGE = ‘0’
FREF_RANGE = ‘1’
1.5
3.0
3.0
5.0
MHz
fPLLOUT
PLL output clock
MX = ”00”
MX = ”01”
MX = ”10”
MX = ”11”
20 x fPLLIN
12 x fPLLIN
28 x fPLLIN
16 x fPLLIN
MHz
fMCLK
System clock
DX = 1..7
fPLLOUT/DX
36
MHz
fFREE
(2)
PLL free running
frequency
FREF_RANGE = ‘0’, MX0 = ’1’
FREF_RANGE = ‘0’, MX0 = ’0’
FREF_RANGE = ‘1’, MX0 = ’1’
FREF_RANGE = ‘1’, MX0 = ’0’
120
240
240
480
kHz
tLOCK
(3)
PLL lock time
stable oscillator
(fPLLIN = 4 MHz), stable VDD
100
300
µs
∆tPKJIT
PLL jitter (pk to pk)
fPLLIN = 4 MHz (pulse
generator)
1.5
ns



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