M41T62 datasheet(13/40 Pages) STMICROELECTRONICS

13 / 40 page

M41T62/63/64/65

Operation

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2.1.4

Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the Low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.1.5

Acknowledge

Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low

level put on the bus by the receiver whereas the master generates an extra acknowledge

related clock pulse. A slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte that has been clocked out of the slave

transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable Low during the High period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line High to enable the master to generate the

STOP condition.

Figure 14.

Serial bus data transfer sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

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