© Semiconductor Components Industries, LLC, 2002

February, 2002 – Rev. 1

1

Publication Order Number:

EB201/D

EB201/D

High Cell Density MOSFETs

Low On–Resistance Affords

New Design Options

Prepared by: Kim Gauen and Wayne Chavez

ON Semiconductor

Just a few years ago an affordable 60 V, 10 m

Ω power

transistor was a dream. After all, 10 m

Ω is the resistance of

about 20 cm of #22 gauge wire. Today a sub–10 m

Ω power

MOSFET is not only available, it is housed in a standard

TO–220. Such are the advances that have occurred lately in

“high

cell

density”

power

MOSFET

technology.

Furthermore, Motorola’s high cell density technology,

HDTMOS

®, brings other advantages such as greatly

improved body diode performance. The technological

advances are sufficiently great that they are fundamentally

changing low voltage power transistor technology.

Cutting the MOSFET’s On–Resistance

A cross section of the power MOSFET is shown in

Figure 1. The major contributors to the standard MOSFET’s

on–resistance

are

its

spreading,

channel,

JFET,

accumulation region, and substrate resistances. To achieve

resistance of all these components. Most of the resistive

elements can be reduced by shrinking cell size and adding

more cells per square centimeter of silicon. However, there

is a limit to maximum packing density. As cell density

becomes very high, on–resistance actually increases due to

a higher JFET resistance. With today’s processes and cell

geometries, the optimum cell density is about five times that

of standard power MOSFETs. Devices built with ON

Semiconductor’s high cell density process (HDTMOS)

in standard power MOSFETs. Figure 2 illustrates the

marked difference in cell density.

R (CH)

GATE

SOURCE

P –

R (JFET)

R(N+)

R (METAL)

R (CONTACT)

R (PACKAGE)

R (ACCUM)

R (SPREAD)

R (BULK)

R (SUBSTRATE)

N + SUBSTRATE

DRAIN

P +

SOURCE

P +

Figure 1. HDTMOS Cross Section

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