EB201/D

http://onsemi.com

3

HIGH CELL

DENSITY

MOSFETs

TO–247

TO–220

or

DPAK

SO–08

DPAK

TO–220

or

TO–247

STANDARD

POWER

MOSFETs

600

5

ON–RESISTANCE

(MILLIOHMS)

50

100

10

A note of caution regarding the use of on–resistance area

products is worthwhile. Lateral DMOS devices have been

shown to have a low on–resistance area product based on

active area, that is, actual MOSFET cell area excluding gate

feeds, bond pads, wirebonds, etc. However, because lateral

DMOS processes have no thick metal capability and

because both the drain and the source contacts must be

routed on the surface of the chip, LDMOS structures pay a

high penalty for bussing current on and off the chip. Based

on total device on–resistance, present LDMOS devices have

about three times the on–resistance–area product of the

newest vertical devices such as the MTP75N05HD.

Manufacturing High Cell Density MOSFETs

Producing power MOSFETs with greater than 2 million cells

per square inch requires an alternative manufacturing method.

A process used for VLSI devices is employed to reduce cell

size and create higher cell densities. The high resolution of this

process is achieved by utilizing positive photoresist and 5X

step–and–repeat projection aligners. In this process the mask

is made 5 times larger to gain line width resolution. Then, when

the image is projected onto the wafer, it is demagnified 5 times,

leaving a crisp and highly resolvable image. The mask is then

stepped along the wafer, and the process is repeated. Together

with VLSI design rules and shallow junction depths, this

self–aligned process is capable of producing cell densities

greater than 5.5 million cells per square inch.

Using the On–Resistance Advantage of HDTMOS

There are several ways to utilize high cell density

technology, but the most attractive is to extend the current

capability of a given power transistor package. For example,

as a TO–220 goes from a 28 m

Ω to a 14 mΩ or 10 mΩ

device, designers can use the lower on–resistance to reduce

junction temperature and improve system efficiency, or to

increase the current capacity of the system. Figure 4 shows

how the on–resistance range of popular packages changes

with the introduction of HDTMOS.

The on–resistance reductions and specifications suggests

one clear use of the technology: applications may be able to

move from larger to smaller packages, which cuts the cost

of the package and decreases the required heatsink or circuit

board area. A good example of this is the 14 m

Ω TO–247.

Until very recently, the only way to achieve such low

on–resistance was to build a large die (on the order of 256 by

256 mils) and place it in the TO–247, which is quite a large

and expensive package. Using HDTMOS, a 14 or even

10 m

Ω die can fit into a TO–220. The smaller, more popular

TO–220 package brings a strong cost advantage.

Similarly, designers may be able to remove a device from

a heatsink and use a free standing device or one that can be

surface mounted instead. An example of this is replacing a

TO–220 with a DPAK (TO–252), or more likely, with a

the on–resistance of the DPAK falls from around 120 to

about 40 m

some engineers will no doubt prefer the smaller, more easily

mountable packages. The development of HDTMOS is

timely since it coincides with the steady improvements in

surface mount substrates (such as metal core boards) which

allow much higher power dissipation. Taken together, the

mechanical and electrical advances can significantly boost

current handling capability of a surface mount module.

Estimates of the current capability of several packages are

shown in Table 1. Calculations are based on the largest die

that a package will house, and the on–resistance of some of

the

SO–8s

and

the

DPAKs

are

projected.

On–resistance–area products of the smallest die sizes are

slightly larger than those of large die sizes due to a

disproportionate penalty for edge terminations, wirebond

pads, and routing of gate feeds. The analysis is based on a

maximum junction temperature appropriate for the

mounting substrate, i.e., devices on heat sinks were allowed

to reach a junction temperature of 150 or 175

°C, whereas

surface mount devices were limited to 125

°C. Junction to

ambient thermal resistance which was used is typical of the

particular mounting method. The first column of figures

shows the maximum rated on–resistance at 25

°C. The

second column shows an estimate of the maximum

allowable current at a junction temperature of either 175 or

125

°C, depending on the mounting method. The

calculations show that HDTMOS gives about a 50%

increase in maximum allowable current.

Another way to compare standard MOSFET technology

and HDTMOS is to note the junction temperature of each

device at a given load current and ambient temperature.

Column 2 of Table 1 shows that HDTMOS will run about 30

to 60

°C cooler than a standard power MOSFET of

equivalent die area. Load current is assumed to be the

amount of current needed to push the HDTMOS device to

125 or 150

°C, depending on mounting method.